mirror of
https://github.com/jankae/LibreVNA.git
synced 2026-01-20 15:40:38 +01:00
Bugfixes autogain
This commit is contained in:
Jan Käberich
parent
f0d4425771
commit
2d3204f908
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@ -116,8 +116,10 @@ END COMPONENT;
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signal p1_gain : std_logic_vector(3 downto 0);
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signal p2_gain : std_logic_vector(3 downto 0);
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signal p1_max : integer range 0 to 65536;
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signal p2_max : integer range 0 to 65536;
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signal p1_max : integer range -16384 to 16383;
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signal p2_max : integer range -16384 to 16383;
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signal p1_min : integer range -16384 to 16383;
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signal p2_min : integer range -16384 to 16383;
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signal autogain_cnt : integer range 0 to AUTOGAIN_SAMPLES + 1;
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signal autogain_changed : std_logic;
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@ -190,6 +192,7 @@ begin
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case state is
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when Idle =>
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sample_cnt <= 0;
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autogain_cnt <= 0;
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '0';
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@ -197,11 +200,13 @@ begin
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phase <= (others => '0');
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mult_enable <= '0';
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mult_accumulate <= "0";
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-- reset peak detector for autogain
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p1_max <= -16384;
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p2_max <= -16384;
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p1_min <= 16383;
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p2_min <= 16383;
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if START = '1' then
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state <= Sampling;
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-- reset peak detector for autogain
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p1_max <= 0;
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p2_max <= 0;
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samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
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end if;
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when Sampling =>
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@ -224,28 +229,34 @@ begin
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if to_integer(signed(PORT1)) > p1_max then
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p1_max <= to_integer(signed(PORT1));
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end if;
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if to_integer(signed(PORT1)) < p1_min then
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p1_min <= to_integer(signed(PORT1));
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end if;
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if to_integer(signed(PORT2)) > p2_max then
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p2_max <= to_integer(signed(PORT2));
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end if;
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if to_integer(signed(PORT2)) < p2_min then
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p2_min <= to_integer(signed(PORT2));
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end if;
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state <= P1Q;
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end if;
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when P1Q =>
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if autogain_cnt = AUTOGAIN_SAMPLES then
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-- check signal range and adjust gain if enabled and necessary
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if PORT1_AUTOGAIN = '1' and p1_max > AUTOGAIN_MAX and p1_gain /= "0000" then
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if PORT1_AUTOGAIN = '1' and p1_max - p1_min > AUTOGAIN_MAX and p1_gain /= "0000" then
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-- signal too high, reduce gain
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autogain_changed <= '1';
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p1_gain <= std_logic_vector(unsigned(p1_gain) - 1);
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elsif PORT1_AUTOGAIN = '1' and p1_max < AUTOGAIN_MIN and p1_gain /= "1000" then
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elsif PORT1_AUTOGAIN = '1' and p1_max - p1_min < AUTOGAIN_MIN and p1_gain /= "1000" then
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-- signal too low, increase gain
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autogain_changed <= '1';
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p1_gain <= std_logic_vector(unsigned(p1_gain) + 1);
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end if;
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if PORT2_AUTOGAIN = '1' and p2_max > AUTOGAIN_MAX and p2_gain /= "0000" then
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if PORT2_AUTOGAIN = '1' and p2_max - p2_min > AUTOGAIN_MAX and p2_gain /= "0000" then
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-- signal too high, reduce gain
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autogain_changed <= '1';
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p2_gain <= std_logic_vector(unsigned(p2_gain) - 1);
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elsif PORT2_AUTOGAIN = '1' and p2_max < AUTOGAIN_MIN and p2_gain /= "1000" then
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elsif PORT2_AUTOGAIN = '1' and p2_max - p2_min < AUTOGAIN_MIN and p2_gain /= "1000" then
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-- signal too low, increase gain
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autogain_changed <= '1';
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p2_gain <= std_logic_vector(unsigned(p2_gain) + 1);
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@ -270,9 +281,14 @@ begin
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state <= P2Q;
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if autogain_changed = '1' then
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-- reset autogain memory and restart sampling process
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p1_max <= 0;
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p2_max <= 0;
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samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
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p1_max <= -16384;
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p2_max <= -16384;
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p1_min <= 16383;
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p2_min <= 16383;
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sample_cnt <= 0;
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autogain_cnt <= 0;
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mult_accumulate <= "0";
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phase <= (others => '0');
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state <= Sampling;
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end if;
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when P2Q =>
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@ -40,7 +40,10 @@ ARCHITECTURE behavior OF Test_Sampling IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Sampling
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Generic(CLK_CYCLES_PRE_DONE : integer);
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Generic(CLK_CYCLES_PRE_DONE : integer;
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AUTOGAIN_SAMPLES : integer;
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AUTOGAIN_MAX : integer;
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AUTOGAIN_MIN : integer);
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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@ -55,13 +58,20 @@ ARCHITECTURE behavior OF Test_Sampling IS
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ADC_START : OUT std_logic;
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DONE : OUT std_logic;
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PRE_DONE : OUT std_logic;
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USEDGAIN : out STD_LOGIC_VECTOR (15 downto 0);
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PORT1_I : OUT std_logic_vector(47 downto 0);
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PORT1_Q : OUT std_logic_vector(47 downto 0);
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PORT2_I : OUT std_logic_vector(47 downto 0);
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PORT2_Q : OUT std_logic_vector(47 downto 0);
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REF_I : OUT std_logic_vector(47 downto 0);
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REF_Q : OUT std_logic_vector(47 downto 0);
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ACTIVE : OUT std_logic
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ACTIVE : OUT std_logic;
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PORT1_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
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PORT1_GAIN_READY : in STD_LOGIC;
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PORT1_AUTOGAIN : in STD_LOGIC;
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PORT2_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
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PORT2_GAIN_READY : in STD_LOGIC;
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PORT2_AUTOGAIN : in STD_LOGIC
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);
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END COMPONENT;
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@ -95,7 +105,10 @@ BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Sampling
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Generic MAP(CLK_CYCLES_PRE_DONE => 0)
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Generic MAP(CLK_CYCLES_PRE_DONE => 0,
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AUTOGAIN_SAMPLES => 16,
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AUTOGAIN_MIN => 2000,
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AUTOGAIN_MAX => 26000)
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PORT MAP (
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CLK => CLK,
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RESET => RESET,
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@ -110,13 +123,20 @@ BEGIN
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ADC_START => ADC_START,
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DONE => DONE,
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PRE_DONE => PRE_DONE,
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USEDGAIN => open,
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PORT1_I => PORT1_I,
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PORT1_Q => PORT1_Q,
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PORT2_I => PORT2_I,
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PORT2_Q => PORT2_Q,
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REF_I => REF_I,
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REF_Q => REF_Q,
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ACTIVE => open
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ACTIVE => open,
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PORT1_GAIN => open,
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PORT1_GAIN_READY => '1',
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PORT1_AUTOGAIN => '1',
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PORT2_GAIN => open,
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PORT2_GAIN_READY => '1',
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PORT2_AUTOGAIN => '1'
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);
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-- Clock process definitions
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@ -139,9 +159,9 @@ BEGIN
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wait for CLK_period*10;
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-- insert stimulus here
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ADC_PRESCALER <= "011110000";
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ADC_PRESCALER <= "11110000";
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PHASEINC <= "010001100000";
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PORT1 <= "000001111111111111";
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PORT1 <= "000000000000111111";
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PORT2 <= "000011111111111111";
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REF <= "000111111111111111";
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SAMPLES <= "0000000000001";
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@ -42,14 +42,14 @@
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MAX9939_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX9939_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MAX9939_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sampling_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Sampling_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sync_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
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@ -139,7 +139,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1622316265" xil_pn:in_ck="-3405005612254819215" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1622316265">
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<transform xil_pn:end_ts="1622473127" xil_pn:in_ck="-3405005612254819215" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1622473127">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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@ -171,15 +171,15 @@
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<outfile xil_pn:name="top.vhd"/>
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<outfile xil_pn:name="window.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1622316001" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2199970647637642169" xil_pn:start_ts="1622316001">
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<transform xil_pn:end_ts="1622472992" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3119389705550358448" xil_pn:start_ts="1622472992">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1622316001" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4636422188803427785" xil_pn:start_ts="1622316001">
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<transform xil_pn:end_ts="1622472992" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="7587375447238577358" xil_pn:start_ts="1622472992">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1622315953" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622315953">
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<transform xil_pn:end_ts="1622472992" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622472992">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
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@ -192,7 +192,7 @@
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<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
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<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1622316265" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1622316265">
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<transform xil_pn:end_ts="1622473127" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1622473127">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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@ -230,30 +230,27 @@
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<outfile xil_pn:name="top.vhd"/>
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<outfile xil_pn:name="window.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1622316267" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="2853946142157696338" xil_pn:start_ts="1622316265">
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<transform xil_pn:end_ts="1622473135" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3971487411785206720" xil_pn:start_ts="1622473127">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForProperties"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="Test_MAX9939_beh.prj"/>
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<outfile xil_pn:name="Test_MAX9939_isim_beh.exe"/>
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<outfile xil_pn:name="Test_Sampling_beh.prj"/>
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<outfile xil_pn:name="Test_Sampling_isim_beh.exe"/>
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<outfile xil_pn:name="fuse.log"/>
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<outfile xil_pn:name="isim"/>
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<outfile xil_pn:name="isim.log"/>
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<outfile xil_pn:name="xilinxsim.ini"/>
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</transform>
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<transform xil_pn:end_ts="1622316267" xil_pn:in_ck="-814711369959840581" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="8409166109357667967" xil_pn:start_ts="1622316267">
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<transform xil_pn:end_ts="1622473135" xil_pn:in_ck="-814711369959840581" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8317794426027222419" xil_pn:start_ts="1622473135">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForProperties"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="Test_MAX9939_isim_beh.wdb"/>
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<outfile xil_pn:name="Test_Sampling_isim_beh.wdb"/>
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<outfile xil_pn:name="isim.cmd"/>
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<outfile xil_pn:name="isim.log"/>
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</transform>
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@ -265,7 +262,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1622319909" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622319909">
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||||
<transform xil_pn:end_ts="1622472676" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622472676">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
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||||
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@ -294,7 +291,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="ReadyToRun"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1622320794" xil_pn:in_ck="-4611116386143726578" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1622320769">
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||||
<transform xil_pn:end_ts="1622489258" xil_pn:in_ck="-4611116386143726578" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1622489233">
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||||
<status xil_pn:value="SuccessfullyRun"/>
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||||
<status xil_pn:value="WarningsGenerated"/>
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||||
<status xil_pn:value="ReadyToRun"/>
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||||
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@ -316,7 +313,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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||||
</transform>
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||||
<transform xil_pn:end_ts="1622320954" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1622320947">
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||||
<transform xil_pn:end_ts="1622489266" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1622489258">
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||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
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||||
<outfile xil_pn:name="_ngo"/>
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||||
|
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@ -325,12 +322,10 @@
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|||
<outfile xil_pn:name="top.ngd"/>
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||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
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||||
</transform>
|
||||
<transform xil_pn:end_ts="1622321048" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1622320954">
|
||||
<transform xil_pn:end_ts="1622489973" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1622489266">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="top.pcf"/>
|
||||
<outfile xil_pn:name="top_map.map"/>
|
||||
|
|
@ -341,7 +336,7 @@
|
|||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1622321079" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1622321048">
|
||||
<transform xil_pn:end_ts="1622490006" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1622489973">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
|
|
@ -355,7 +350,7 @@
|
|||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1622321094" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1622321079">
|
||||
<transform xil_pn:end_ts="1622490022" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1622490006">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -409,7 +404,7 @@
|
|||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1622321079" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1622321072">
|
||||
<transform xil_pn:end_ts="1622490006" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1622489998">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
|
|
|
|||
|
|
@ -41,15 +41,15 @@
|
|||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="49"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
|
||||
|
|
@ -133,7 +133,7 @@
|
|||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/DSP_SLICE.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="Windowing.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
|
@ -147,11 +147,11 @@
|
|||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
|
||||
</file>
|
||||
<file xil_pn:name="MAX9939.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MAX9939.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="165"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="165"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="165"/>
|
||||
|
|
@ -415,8 +415,8 @@
|
|||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top/SA_DFT" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.DFT" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Sampling" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_Sampling" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -434,7 +434,7 @@
|
|||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.DFT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_Sampling" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
|
@ -486,7 +486,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MAX9939|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Sampling|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
|
|
|||
BIN
FPGA/VNA/top.bin
BIN
FPGA/VNA/top.bin
Binary file not shown.
|
|
@ -680,8 +680,8 @@ begin
|
|||
Sampler: Sampling
|
||||
GENERIC MAP(CLK_CYCLES_PRE_DONE => 0,
|
||||
AUTOGAIN_SAMPLES => 16,
|
||||
AUTOGAIN_MIN => 7000,
|
||||
AUTOGAIN_MAX => 140000)
|
||||
AUTOGAIN_MIN => 2000,
|
||||
AUTOGAIN_MAX => 26000)
|
||||
PORT MAP(
|
||||
CLK => clk160,
|
||||
RESET => sweep_reset,
|
||||
|
|
|
|||
|
|
@ -256,7 +256,7 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
|
|||
return false;
|
||||
}
|
||||
callback = cb;
|
||||
uint8_t cmd[40] = {0xC0, 0x00};
|
||||
uint8_t cmd[42] = {0xC0, 0x00};
|
||||
// Start data read
|
||||
Low(CS);
|
||||
busy_reading = true;
|
||||
|
|
|
|||
|
|
@ -76,6 +76,8 @@ void Manual::Setup(Protocol::ManualControl m) {
|
|||
// Enable new data and sweep halt interrupt
|
||||
FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
|
||||
|
||||
FPGA::SetAutogain();
|
||||
|
||||
active = true;
|
||||
FPGA::StartSweep();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
|
|||
}
|
||||
|
||||
FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
|
||||
LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20,
|
||||
LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us540,
|
||||
FPGA::Samples::SPPRegister, needs_halt);
|
||||
last_lowband = lowband;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue