diff --git a/FPGA/VNA/Sampling.vhd b/FPGA/VNA/Sampling.vhd
index 847e05c..78f6d7f 100644
--- a/FPGA/VNA/Sampling.vhd
+++ b/FPGA/VNA/Sampling.vhd
@@ -116,8 +116,10 @@ END COMPONENT;
 	
 	signal p1_gain : std_logic_vector(3 downto 0);
 	signal p2_gain : std_logic_vector(3 downto 0);
-	signal p1_max : integer range 0 to 65536;
-	signal p2_max : integer range 0 to 65536;
+	signal p1_max : integer range -16384 to 16383;
+	signal p2_max : integer range -16384 to 16383;
+	signal p1_min : integer range -16384 to 16383;
+	signal p2_min : integer range -16384 to 16383;
 	
 	signal autogain_cnt : integer range 0 to AUTOGAIN_SAMPLES + 1;
 	signal autogain_changed : std_logic;
@@ -190,6 +192,7 @@ begin
 				case state is
 					when Idle =>
 						sample_cnt <= 0;
+						autogain_cnt <= 0;
 						DONE <= '0';
 						PRE_DONE <= '0';
 						ACTIVE <= '0';
@@ -197,11 +200,13 @@ begin
 						phase <= (others => '0');
 						mult_enable <= '0';
 						mult_accumulate <= "0";
+						-- reset peak detector for autogain
+						p1_max <= -16384;
+						p2_max <= -16384;
+						p1_min <= 16383;
+						p2_min <= 16383;
 						if START = '1' then
 							state <= Sampling;
-							-- reset peak detector for autogain
-							p1_max <= 0;
-							p2_max <= 0;
 							samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
 						end if;
 					when Sampling =>
@@ -224,28 +229,34 @@ begin
 							if to_integer(signed(PORT1)) > p1_max then
 								p1_max <= to_integer(signed(PORT1));
 							end if;
+							if to_integer(signed(PORT1)) < p1_min then
+								p1_min <= to_integer(signed(PORT1));
+							end if;
 							if to_integer(signed(PORT2)) > p2_max then
 								p2_max <= to_integer(signed(PORT2));
 							end if;
+							if to_integer(signed(PORT2)) < p2_min then
+								p2_min <= to_integer(signed(PORT2));
+							end if;
 							state <= P1Q;
 						end if;
 					when P1Q =>
 						if autogain_cnt = AUTOGAIN_SAMPLES then
 							-- check signal range and adjust gain if enabled and necessary
-							if PORT1_AUTOGAIN = '1' and p1_max > AUTOGAIN_MAX and p1_gain /= "0000" then
+							if PORT1_AUTOGAIN = '1' and p1_max - p1_min > AUTOGAIN_MAX and p1_gain /= "0000" then
 								-- signal too high, reduce gain
 								autogain_changed <= '1';
 								p1_gain <= std_logic_vector(unsigned(p1_gain) - 1);
-							elsif PORT1_AUTOGAIN = '1' and p1_max < AUTOGAIN_MIN and p1_gain /= "1000" then
+							elsif PORT1_AUTOGAIN = '1' and p1_max - p1_min < AUTOGAIN_MIN and p1_gain /= "1000" then
 								-- signal too low, increase gain
 								autogain_changed <= '1';
 								p1_gain <= std_logic_vector(unsigned(p1_gain) + 1);
 							end if;
-							if PORT2_AUTOGAIN = '1' and p2_max > AUTOGAIN_MAX and p2_gain /= "0000" then
+							if PORT2_AUTOGAIN = '1' and p2_max - p2_min > AUTOGAIN_MAX and p2_gain /= "0000" then
 								-- signal too high, reduce gain
 								autogain_changed <= '1';
 								p2_gain <= std_logic_vector(unsigned(p2_gain) - 1);
-							elsif PORT2_AUTOGAIN = '1' and p2_max < AUTOGAIN_MIN and p2_gain /= "1000" then
+							elsif PORT2_AUTOGAIN = '1' and p2_max - p2_min < AUTOGAIN_MIN and p2_gain /= "1000" then
 								-- signal too low, increase gain
 								autogain_changed <= '1';
 								p2_gain <= std_logic_vector(unsigned(p2_gain) + 1);
@@ -270,9 +281,14 @@ begin
 						state <= P2Q;
 						if autogain_changed = '1' then
 							-- reset autogain memory and restart sampling process
-							p1_max <= 0;
-							p2_max <= 0;
-							samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
+							p1_max <= -16384;
+							p2_max <= -16384;
+							p1_min <= 16383;
+							p2_min <= 16383;
+							sample_cnt <= 0;
+							autogain_cnt <= 0;
+							mult_accumulate <= "0";
+							phase <= (others => '0');
 							state <= Sampling;
 						end if;
 					when P2Q =>
diff --git a/FPGA/VNA/Test_Sampling.vhd b/FPGA/VNA/Test_Sampling.vhd
index b56f330..3b5c7c6 100644
--- a/FPGA/VNA/Test_Sampling.vhd
+++ b/FPGA/VNA/Test_Sampling.vhd
@@ -40,7 +40,10 @@ ARCHITECTURE behavior OF Test_Sampling IS
     -- Component Declaration for the Unit Under Test (UUT)
  
     COMPONENT Sampling
-	 Generic(CLK_CYCLES_PRE_DONE : integer);
+	 Generic(CLK_CYCLES_PRE_DONE : integer;
+				AUTOGAIN_SAMPLES : integer;
+				AUTOGAIN_MAX : integer;
+				AUTOGAIN_MIN : integer);
 	PORT(
 		CLK : IN std_logic;
 		RESET : IN std_logic;
@@ -55,13 +58,20 @@ ARCHITECTURE behavior OF Test_Sampling IS
 		ADC_START : OUT std_logic;
 		DONE : OUT std_logic;
 		PRE_DONE : OUT std_logic;
+		USEDGAIN : out STD_LOGIC_VECTOR (15 downto 0);
 		PORT1_I : OUT std_logic_vector(47 downto 0);
 		PORT1_Q : OUT std_logic_vector(47 downto 0);
 		PORT2_I : OUT std_logic_vector(47 downto 0);
 		PORT2_Q : OUT std_logic_vector(47 downto 0);
 		REF_I : OUT std_logic_vector(47 downto 0);
 		REF_Q : OUT std_logic_vector(47 downto 0);
-		ACTIVE : OUT std_logic
+		ACTIVE : OUT std_logic;
+		PORT1_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
+		PORT1_GAIN_READY : in STD_LOGIC;
+		PORT1_AUTOGAIN : in STD_LOGIC;
+		PORT2_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
+		PORT2_GAIN_READY : in STD_LOGIC;
+		PORT2_AUTOGAIN : in STD_LOGIC
 		);
     END COMPONENT;
     
@@ -95,7 +105,10 @@ BEGIN
  
 	-- Instantiate the Unit Under Test (UUT)
    uut: Sampling
-	Generic MAP(CLK_CYCLES_PRE_DONE => 0)
+	Generic MAP(CLK_CYCLES_PRE_DONE => 0,
+					AUTOGAIN_SAMPLES => 16,
+					AUTOGAIN_MIN => 2000,
+					AUTOGAIN_MAX => 26000)
 	PORT MAP (
 			CLK => CLK,
 			RESET => RESET,
@@ -110,13 +123,20 @@ BEGIN
 			ADC_START => ADC_START,
 			DONE => DONE,
 			PRE_DONE => PRE_DONE,
+			USEDGAIN => open,
 			PORT1_I => PORT1_I,
 			PORT1_Q => PORT1_Q,
 			PORT2_I => PORT2_I,
 			PORT2_Q => PORT2_Q,
 			REF_I => REF_I,
 			REF_Q => REF_Q,
-			ACTIVE => open
+			ACTIVE => open,
+			PORT1_GAIN => open,
+			PORT1_GAIN_READY => '1',
+			PORT1_AUTOGAIN => '1',
+			PORT2_GAIN => open,
+			PORT2_GAIN_READY => '1',
+			PORT2_AUTOGAIN => '1'
         );
 
    -- Clock process definitions
@@ -139,9 +159,9 @@ BEGIN
       wait for CLK_period*10;
 
       -- insert stimulus here
-		ADC_PRESCALER <= "011110000";
+		ADC_PRESCALER <= "11110000";
 		PHASEINC <= "010001100000";
-		PORT1 <= "000001111111111111";
+		PORT1 <= "000000000000111111";
 		PORT2 <= "000011111111111111";
 		REF <= "000111111111111111";
 		SAMPLES <= "0000000000001";
diff --git a/FPGA/VNA/VNA.gise b/FPGA/VNA/VNA.gise
index a014671..6c3421e 100644
--- a/FPGA/VNA/VNA.gise
+++ b/FPGA/VNA/VNA.gise
@@ -42,14 +42,14 @@
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MAX9939_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX9939_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MAX9939_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sampling_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Sampling_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sync_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
@@ -139,7 +139,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1622316265" xil_pn:in_ck="-3405005612254819215" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1622316265">
+    <transform xil_pn:end_ts="1622473127" xil_pn:in_ck="-3405005612254819215" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1622473127">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -171,15 +171,15 @@
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1622316001" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2199970647637642169" xil_pn:start_ts="1622316001">
+    <transform xil_pn:end_ts="1622472992" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-3119389705550358448" xil_pn:start_ts="1622472992">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1622316001" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4636422188803427785" xil_pn:start_ts="1622316001">
+    <transform xil_pn:end_ts="1622472992" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="7587375447238577358" xil_pn:start_ts="1622472992">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1622315953" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622315953">
+    <transform xil_pn:end_ts="1622472992" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622472992">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@@ -192,7 +192,7 @@
       <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
       <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1622316265" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1622316265">
+    <transform xil_pn:end_ts="1622473127" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1622473127">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -230,30 +230,27 @@
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1622316267" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="2853946142157696338" xil_pn:start_ts="1622316265">
+    <transform xil_pn:end_ts="1622473135" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3971487411785206720" xil_pn:start_ts="1622473127">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForProperties"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_MAX9939_beh.prj"/>
-      <outfile xil_pn:name="Test_MAX9939_isim_beh.exe"/>
+      <outfile xil_pn:name="Test_Sampling_beh.prj"/>
+      <outfile xil_pn:name="Test_Sampling_isim_beh.exe"/>
       <outfile xil_pn:name="fuse.log"/>
       <outfile xil_pn:name="isim"/>
-      <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1622316267" xil_pn:in_ck="-814711369959840581" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="8409166109357667967" xil_pn:start_ts="1622316267">
+    <transform xil_pn:end_ts="1622473135" xil_pn:in_ck="-814711369959840581" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8317794426027222419" xil_pn:start_ts="1622473135">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForProperties"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_MAX9939_isim_beh.wdb"/>
+      <outfile xil_pn:name="Test_Sampling_isim_beh.wdb"/>
       <outfile xil_pn:name="isim.cmd"/>
       <outfile xil_pn:name="isim.log"/>
     </transform>
@@ -265,7 +262,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1622319909" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622319909">
+    <transform xil_pn:end_ts="1622472676" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622472676">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@@ -294,7 +291,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1622320794" xil_pn:in_ck="-4611116386143726578" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1622320769">
+    <transform xil_pn:end_ts="1622489258" xil_pn:in_ck="-4611116386143726578" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1622489233">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -316,7 +313,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1622320954" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1622320947">
+    <transform xil_pn:end_ts="1622489266" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1622489258">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -325,12 +322,10 @@
       <outfile xil_pn:name="top.ngd"/>
       <outfile xil_pn:name="top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1622321048" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1622320954">
+    <transform xil_pn:end_ts="1622489973" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1622489266">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
       <outfile xil_pn:name="top.pcf"/>
       <outfile xil_pn:name="top_map.map"/>
@@ -341,7 +336,7 @@
       <outfile xil_pn:name="top_summary.xml"/>
       <outfile xil_pn:name="top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1622321079" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1622321048">
+    <transform xil_pn:end_ts="1622490006" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1622489973">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -355,7 +350,7 @@
       <outfile xil_pn:name="top_pad.txt"/>
       <outfile xil_pn:name="top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1622321094" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1622321079">
+    <transform xil_pn:end_ts="1622490022" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1622490006">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -409,7 +404,7 @@
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="InputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1622321079" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1622321072">
+    <transform xil_pn:end_ts="1622490006" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1622489998">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
diff --git a/FPGA/VNA/VNA.xise b/FPGA/VNA/VNA.xise
index 4a9efc7..49fa10c 100644
--- a/FPGA/VNA/VNA.xise
+++ b/FPGA/VNA/VNA.xise
@@ -41,15 +41,15 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="49"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="49"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
@@ -133,7 +133,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="ipcore_dir/DSP_SLICE.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="Windowing.vhd" xil_pn:type="FILE_VHDL">
@@ -147,11 +147,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
     </file>
     <file xil_pn:name="MAX9939.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="Test_MAX9939.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="165"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="165"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="165"/>
@@ -415,8 +415,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top/SA_DFT" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.DFT" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Sampling" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_Sampling" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -434,7 +434,7 @@
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.DFT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_Sampling" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -486,7 +486,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MAX9939|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Sampling|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
diff --git a/FPGA/VNA/top.bin b/FPGA/VNA/top.bin
index e01a468..abc96c9 100644
Binary files a/FPGA/VNA/top.bin and b/FPGA/VNA/top.bin differ
diff --git a/FPGA/VNA/top.vhd b/FPGA/VNA/top.vhd
index a574664..358a35b 100644
--- a/FPGA/VNA/top.vhd
+++ b/FPGA/VNA/top.vhd
@@ -680,8 +680,8 @@ begin
 	Sampler: Sampling
 	GENERIC MAP(CLK_CYCLES_PRE_DONE => 0,
 					AUTOGAIN_SAMPLES => 16,
-					AUTOGAIN_MIN => 7000,
-					AUTOGAIN_MAX => 140000)
+					AUTOGAIN_MIN => 2000,
+					AUTOGAIN_MAX => 26000)
 	PORT MAP(
 		CLK => clk160,
 		RESET => sweep_reset,
diff --git a/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp b/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
index 6dc5507..3c69436 100644
--- a/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
+++ b/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
@@ -256,7 +256,7 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
 		return false;
 	}
 	callback = cb;
-	uint8_t cmd[40] = {0xC0, 0x00};
+	uint8_t cmd[42] = {0xC0, 0x00};
 	// Start data read
 	Low(CS);
 	busy_reading = true;
diff --git a/Software/VNA_embedded/Application/Manual.cpp b/Software/VNA_embedded/Application/Manual.cpp
index 9229457..a7f8bc3 100644
--- a/Software/VNA_embedded/Application/Manual.cpp
+++ b/Software/VNA_embedded/Application/Manual.cpp
@@ -76,6 +76,8 @@ void Manual::Setup(Protocol::ManualControl m) {
 	// Enable new data and sweep halt interrupt
 	FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
 
+	FPGA::SetAutogain();
+
 	active = true;
 	FPGA::StartSweep();
 }
diff --git a/Software/VNA_embedded/Application/VNA.cpp b/Software/VNA_embedded/Application/VNA.cpp
index 204a6ca..dceb5d4 100644
--- a/Software/VNA_embedded/Application/VNA.cpp
+++ b/Software/VNA_embedded/Application/VNA.cpp
@@ -207,7 +207,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
 		}
 
 		FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
-				LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20,
+				LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us540,
 				FPGA::Samples::SPPRegister, needs_halt);
 		last_lowband = lowband;
 	}