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Adapted to experimental FPGA protocol with autogain

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This commit is contained in:
Jan Käberich 2021-05-29 23:44:59 +02:00
parent 4d1a409969
commit f0d4425771
4 changed files with 32 additions and 2 deletions
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19
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
View file

@ -13,6 +13,7 @@
static FPGA::HaltedCallback halted_cb;
static uint16_t SysCtrlReg = 0x0000;
static uint16_t ISRMaskReg = 0x0000;
static uint16_t GainReg = 0x0000;
static uint32_t ADC_samplerate;
using namespace FPGAHAL;
@ -88,6 +89,8 @@ bool FPGA::Init(HaltedCallback cb) {
halted_cb = cb;
SysCtrlReg = 0;
ISRMaskReg = 0;
GainReg = 0;
// Reset FPGA
High(FPGA_RESET);
SetMode(Mode::FPGA);
@ -243,7 +246,7 @@ static inline int64_t sign_extend_64(int64_t x, uint16_t bits) {
}
static FPGA::ReadCallback callback;
static uint8_t raw[40];
static uint8_t raw[42];
static FPGA::SamplingResult result;
static bool busy_reading = false;
@ -257,7 +260,7 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
// Start data read
Low(CS);
busy_reading = true;
HAL_SPI_TransmitReceive_DMA(&FPGA_SPI, cmd, raw, 40);
HAL_SPI_TransmitReceive_DMA(&FPGA_SPI, cmd, raw, 42);
return true;
}
@ -281,6 +284,8 @@ void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
result.RefQ = assembleSampleResultValue(&raw[2]);
result.pointNum = (uint16_t)(raw[38]&0x1F) << 8 | raw[39];
result.activePort = raw[38] & 0x80 ? 1 : 0;
result.P1gain = raw[41] & 0x0F;
result.P2gain = raw[41] >> 4;
High(CS);
busy_reading = false;
if ((status & 0x0004) && callback) {
@ -415,3 +420,13 @@ FPGA::DFTResult FPGA::ReadDFTResult() {
res.P2 = std::abs(p2);
return res;
}
void FPGA::SetAutogain() {
GainReg |= 0x3000;
WriteRegister(Reg::PGAGain, GainReg);
}
void FPGA::SetManualGain(uint8_t p1gain, uint8_t p2gain) {
GainReg = (p1gain & 0x0F) | (p2gain & 0x0F) << 4;
WriteRegister(Reg::PGAGain, GainReg);
}

5
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
View file

@ -16,6 +16,7 @@ enum class Reg {
SystemControl = 0x03,
ADCPrescaler = 0x04,
PhaseIncrement = 0x05,
PGAGain = 0x06,
MAX2871Def0LSB = 0x08,
MAX2871Def0MSB = 0x09,
MAX2871Def1LSB = 0x0A,
@ -34,6 +35,8 @@ using SamplingResult = struct _samplingresult {
int64_t RefI, RefQ;
uint16_t pointNum :15;
uint16_t activePort :1;
uint8_t P1gain :4;
uint8_t P2gain :4;
};
using DFTResult = struct _dftresult {
@ -114,6 +117,8 @@ void SetNumberOfPoints(uint16_t npoints);
void SetSamplesPerPoint(uint32_t nsamples);
void Enable(Periphery p, bool enable = true);
void Disable(Periphery p);
void SetAutogain();
void SetManualGain(uint8_t p1gain, uint8_t p2gain);
bool IsEnabled(Periphery p);
void SetWindow(Window w);
void EnableInterrupt(Interrupt i);

3
Software/VNA_embedded/Application/Hardware.cpp
View file

@ -177,6 +177,9 @@ bool HW::Init() {
FPGA::Disable(FPGA::Periphery::LO1Chip);
FPGA::WriteMAX2871Default(Source.GetRegisters());
// Set default gain (1V/V)
FPGA::SetManualGain(0, 0);
LOG_INFO("Initialized");
FPGA::Enable(FPGA::Periphery::ReadyLED);

7
Software/VNA_embedded/Application/VNA.cpp
View file

@ -227,6 +227,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
FPGA::Enable(FPGA::Periphery::ExcitePort1, s.excitePort1);
FPGA::Enable(FPGA::Periphery::ExcitePort2, s.excitePort2);
FPGA::Enable(FPGA::Periphery::PortSwitch);
FPGA::SetAutogain();
pointCnt = 0;
// starting port depends on whether port 1 is active in sweep
excitingPort1 = s.excitePort1;
@ -260,6 +261,12 @@ bool VNA::MeasurementDone(const FPGA::SamplingResult &result) {
// normal sweep mode
auto port1_raw = std::complex<float>(result.P1I, result.P1Q);
auto port2_raw = std::complex<float>(result.P2I, result.P2Q);
// correct applied gain
constexpr uint8_t gainValues[] = {1, 10, 20, 30, 40, 60, 80, 120, 157};
port1_raw /= gainValues[result.P1gain];
port2_raw /= gainValues[result.P2gain];
auto ref = std::complex<float>(result.RefI, result.RefQ);
auto port1 = port1_raw / ref;
auto port2 = port2_raw / ref;