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First attempt at MAX9939 autogain implementation
This commit is contained in:
Jan Käberich
parent
34a24abb40
commit
4d1a409969
Binary file not shown.
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@ -147,7 +147,7 @@ Initiate the reading of sampling data by sending the command word:
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\robits{3}{13}{reserved}
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\end{tikzpicture}
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\end{center}
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Afterwards, read up to 19 words before setting NSS high. These 19 words will contain the sampling result (see section~\ref{result}), transmitted with the least significant word first.
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Afterwards, read up to 20 words before setting NSS high. These 20 words will contain the sampling result (see section~\ref{result}), transmitted with the least significant word first.
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\subsection{Resuming a halted sweep}
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When the halt bit is set in the SweepConfig, the FPGA will configure the Source and LO as requested but will not start the settling timer (and subsequently the sampling process) until this resume command is issued. The halted sweep is indicated by the sweep halted bit in the status register.
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@ -405,6 +405,42 @@ $$ PhaseInc = \frac{4096 * f_{IF2}}{SR_{ADC}} $$
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For the the default IF frequency of $f_{IF2} = \SI{250}{\kilo\hertz}$ this evaluates to 10*Presc (see ADC prescaler register).
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\end{itemize}
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\subsection{PGA gain settings: 0x06}
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\label{reg:pgagain}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\robits{0}{2}{reserved}
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\rwbits{2}{1}{P2AG}
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\rwbits{3}{1}{P1AG}
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\robits{4}{4}{reserved}
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\rwbits{8}{4}{Port 2 gain[3:0]}
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\rwbits{12}{4}{Port 1 gain[3:0]}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{P2AG:} Autogain enable for ADC at port 2. During each sampling point, the first few initial ADC samples are evaluated and the gain of the PGA adjusted if necessary. Autogain only works correctly when a rectangular window is used.
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\item \textbf{P1AG:} Autogain enable for ADC at port 1.
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\item \textbf{Port 2 gain[3:0]:} Gain selection for port 2 PGA, only used when autogain is disabled.
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\begin{center}
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\begin{tabular}{ c|c }
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Setting & Gain (V/V)\\
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\hline
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0000 & 1\\
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0001 & 10\\
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0010 & 20\\
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0011 & 30\\
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0100 & 40\\
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0101 & 60\\
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0110 & 80\\
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0111 & 120\\
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1000 & 157\\
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1001--1111 & Reserved\\
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\end{tabular}
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\end{center}
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\item \textbf{Port 1 gain[3:0]:} Gain selection for port 1 PGA, only used when autogain is disabled. Same gain values available as for port 2.
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\end{itemize}
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\subsection{MAX2871 Default Values Registers: 0x08-0x0F}
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See datasheet of MAX2871 for bit descriptions. Bits for the fields N, FRAC, M, VCO and DIV\_A are "don't care" as they will be overwritten by the SweepConfig setting.
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\begin{center}
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@ -562,6 +598,12 @@ Setting & Selected Band\\
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Each point in the sweep generates two sampling results. The first one contains the measurement when the source was routed to Port 1, the second sampling result was taken when the source was routed to Port 2.
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{320-\bit}
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\rwbits{0}{8}{reserved}
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\robits{8}{4}{Port 2 gain [3:0]}
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\rwbits{12}{4}{Port 1 gain [3:0]}
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\end{tikzpicture}
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\begin{tikzpicture}
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\bitrect{16}{304-\bit}
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\rwbits{0}{1}{SRC}
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\robits{1}{2}{reserved}
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@ -646,4 +688,11 @@ Each point in the sweep generates two sampling results. The first one contains t
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{Port 2 gain:} Used gain setting for port 2 if autoranging is enabled. Meaningless if autoranging is disabled. See section~\ref{reg:pgagain} for the mapping of gain factors to the bits.
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\item \textbf{Port 1 gain:} Used gain setting for port 1 if autoranging is enabled. Meaningless if autoranging is disabled. See section~\ref{reg:pgagain} for the mapping of gain factors to the bits.
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\item \textbf{SRC:} 0 if port 1 was excited during the measurement, 1 if port 2 was excited.
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\item \textbf{POINT\_NUMBER[12:0]:} Indicates the sampling point in the sweep from which the result was acquired (used for verification purposes).
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\end{itemize}
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\end{document}
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107
FPGA/VNA/MAX9939.vhd
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107
FPGA/VNA/MAX9939.vhd
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@ -0,0 +1,107 @@
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:59:58 05/29/2021
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-- Design Name:
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-- Module Name: MAX9939 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity MAX9939 is
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Generic(CLK_DIV : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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GAIN : in STD_LOGIC_VECTOR (3 downto 0);
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READY : out STD_LOGIC;
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CS : out STD_LOGIC;
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SCLK : out STD_LOGIC;
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DIN : out STD_LOGIC);
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end MAX9939;
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architecture Behavioral of MAX9939 is
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signal div_cnt : integer range 0 to (CLK_DIV/2)-1;
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signal chip_select : std_logic;
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type States is (Idle, CLKlow, CLKhigh);
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signal shift_register : std_logic_vector(7 downto 0);
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signal bitcount : integer range 0 to 8;
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signal state : States;
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signal current_gain : std_logic_vector(3 downto 0);
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begin
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READY <= chip_select;
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CS <= chip_select;
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process(CLK, RESET)
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begin
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if(rising_edge(CLK)) then
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DIN <= shift_register(0);
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if(RESET = '1') then
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state <= Idle;
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chip_select <= '1';
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SCLK <= '0';
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current_gain <= "1111"; -- this is an invalid value, any valid value at GAIN input will trigger the transfer
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else
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case state is
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when Idle =>
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SCLK <= '0';
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chip_select <= '1';
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if(current_gain /= GAIN) then
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current_gain <= GAIN;
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shift_register <= "000" & GAIN & "1";
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bitcount <= 0;
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state <= CLKlow;
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div_cnt <= 0;
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end if;
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when CLKlow =>
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SCLK <= '0';
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chip_select <= '0';
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if div_cnt = CLK_DIV/2 - 1 then
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if bitcount = 8 then
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state <= Idle;
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else
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bitcount <= bitcount + 1;
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div_cnt <= 0;
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state <= CLKhigh;
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end if;
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else
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div_cnt <= div_cnt + 1;
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end if;
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when CLKhigh =>
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SCLK <= '1';
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chip_select <= '0';
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if div_cnt = CLK_DIV/2 - 1 then
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div_cnt <= 0;
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state <= CLKlow;
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shift_register <= "0" & shift_register(7 downto 1);
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else
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div_cnt <= div_cnt + 1;
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end if;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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@ -37,7 +37,7 @@ entity SPICommands is
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MISO : out STD_LOGIC;
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NSS : in STD_LOGIC;
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NEW_SAMPLING_DATA : in STD_LOGIC;
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SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
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SAMPLING_RESULT : in STD_LOGIC_VECTOR (319 downto 0);
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ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
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SOURCE_UNLOCKED : in STD_LOGIC;
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LO_UNLOCKED : in STD_LOGIC;
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@ -77,7 +77,13 @@ entity SPICommands is
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DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
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DFT_NEXT_OUTPUT : out STD_LOGIC;
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DFT_ENABLE : out STD_LOGIC;
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-- ADC gain settings
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PORT1_GAIN : out STD_LOGIC_VECTOR(3 downto 0); -- only used when autogain disabled
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PORT2_GAIN : out STD_LOGIC_VECTOR(3 downto 0); -- only used when autogain disabled
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PORT1_AUTOGAIN : out STD_LOGIC;
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PORT2_AUTOGAIN : out STD_LOGIC;
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DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
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end SPICommands;
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@ -116,7 +122,7 @@ architecture Behavioral of SPICommands is
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signal interrupt_mask : std_logic_vector(15 downto 0);
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signal interrupt_status : std_logic_vector(15 downto 0);
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signal latched_result : std_logic_vector(287 downto 0);
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signal latched_result : std_logic_vector(303 downto 0);
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signal sweepconfig_buffer : std_logic_vector(79 downto 0);
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begin
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SPI: spi_slave
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@ -218,7 +224,7 @@ begin
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spi_buf_in <= DFT_OUTPUT(15 downto 0);
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dft_next <= '1';
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when "110" => state <= ReadResult;
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latched_result <= SAMPLING_RESULT(303 downto 16);
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latched_result <= SAMPLING_RESULT(319 downto 16);
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spi_buf_in <= SAMPLING_RESULT(15 downto 0);
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unread_sampling_data <= '0';
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when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
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@ -247,6 +253,10 @@ begin
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EXCITE_PORT2 <= spi_buf_out(2);
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when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
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when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
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when 6 => PORT1_GAIN <= spi_buf_out(3 downto 0);
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PORT2_GAIN <= spi_buf_out(7 downto 4);
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PORT1_AUTOGAIN <= spi_buf_out(12);
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PORT2_AUTOGAIN <= spi_buf_out(13);
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when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
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when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
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when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
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@ -272,7 +282,7 @@ begin
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when ReadResult =>
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-- pass on next word of latched result
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spi_buf_in <= latched_result(15 downto 0);
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latched_result <= "0000000000000000" & latched_result(287 downto 16);
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latched_result <= "0000000000000000" & latched_result(303 downto 16);
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end case;
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end if;
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end if;
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@ -30,7 +30,10 @@ use IEEE.NUMERIC_STD.ALL;
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--use UNISIM.VComponents.all;
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entity Sampling is
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Generic(CLK_CYCLES_PRE_DONE : integer);
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Generic(CLK_CYCLES_PRE_DONE : integer;
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AUTOGAIN_SAMPLES : integer;
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AUTOGAIN_MAX : integer;
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AUTOGAIN_MIN : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
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@ -42,6 +45,7 @@ entity Sampling is
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NEW_SAMPLE : in STD_LOGIC;
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DONE : out STD_LOGIC;
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PRE_DONE : out STD_LOGIC;
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USEDGAIN : out STD_LOGIC_VECTOR (15 downto 0);
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START : in STD_LOGIC;
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SAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
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PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
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@ -50,7 +54,13 @@ entity Sampling is
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PORT2_Q : out STD_LOGIC_VECTOR (47 downto 0);
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REF_I : out STD_LOGIC_VECTOR (47 downto 0);
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REF_Q : out STD_LOGIC_VECTOR (47 downto 0);
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ACTIVE : out STD_LOGIC);
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ACTIVE : out STD_LOGIC;
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PORT1_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
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PORT1_GAIN_READY : in STD_LOGIC;
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PORT1_AUTOGAIN : in STD_LOGIC;
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PORT2_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
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PORT2_GAIN_READY : in STD_LOGIC;
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PORT2_AUTOGAIN : in STD_LOGIC);
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end Sampling;
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architecture Behavioral of Sampling is
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@ -104,6 +114,14 @@ END COMPONENT;
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signal mult_enable : std_logic;
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signal mult_accumulate : std_logic_vector(0 downto 0);
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signal p1_gain : std_logic_vector(3 downto 0);
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signal p2_gain : std_logic_vector(3 downto 0);
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signal p1_max : integer range 0 to 65536;
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signal p2_max : integer range 0 to 65536;
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signal autogain_cnt : integer range 0 to AUTOGAIN_SAMPLES + 1;
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signal autogain_changed : std_logic;
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type States is (Idle, Sampling, P1Q, P2I, P2Q, RI, RQ, SaveP1Q, SaveP2I, SaveP2Q, SaveRI, SaveRQ, Ready);
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signal state : States;
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begin
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@ -134,6 +152,9 @@ begin
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-- sign extend b input of multiplier (sin/cos)
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mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
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PORT1_GAIN <= p1_gain;
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PORT2_GAIN <= p2_gain;
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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@ -148,6 +169,8 @@ begin
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phase <= (others => '0');
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mult_enable <= '0';
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mult_accumulate <= "0";
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p1_gain <= "0000";
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p2_gain <= "0000";
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else
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-- when not idle, generate pulses for ADCs
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if state /= Idle then
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@ -176,6 +199,9 @@ begin
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mult_accumulate <= "0";
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if START = '1' then
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state <= Sampling;
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-- reset peak detector for autogain
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p1_max <= 0;
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p2_max <= 0;
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samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
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end if;
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when Sampling =>
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@ -183,15 +209,48 @@ begin
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PRE_DONE <= '0';
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ACTIVE <= '1';
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mult_enable <= '0';
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if NEW_SAMPLE = '1' then
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-- only accept new samples when the gain has been transferred to the PGA
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if NEW_SAMPLE = '1' and PORT1_GAIN_READY = '1' and PORT2_GAIN_READY = '1' then
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sample_cnt <= sample_cnt + 1;
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if autogain_cnt /= AUTOGAIN_SAMPLES + 1 then
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autogain_cnt <= autogain_cnt + 1;
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end if;
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autogain_changed <= '0';
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mult_enable <= '1';
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mult_a <= PORT1;
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mult_b(15 downto 0) <= cosine;
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mult_c <= p1_I;
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-- keep track of maximum value for autogain
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if to_integer(signed(PORT1)) > p1_max then
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p1_max <= to_integer(signed(PORT1));
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end if;
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if to_integer(signed(PORT2)) > p2_max then
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p2_max <= to_integer(signed(PORT2));
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end if;
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state <= P1Q;
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end if;
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when P1Q =>
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if autogain_cnt = AUTOGAIN_SAMPLES then
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-- check signal range and adjust gain if enabled and necessary
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if PORT1_AUTOGAIN = '1' and p1_max > AUTOGAIN_MAX and p1_gain /= "0000" then
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-- signal too high, reduce gain
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autogain_changed <= '1';
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p1_gain <= std_logic_vector(unsigned(p1_gain) - 1);
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elsif PORT1_AUTOGAIN = '1' and p1_max < AUTOGAIN_MIN and p1_gain /= "1000" then
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-- signal too low, increase gain
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autogain_changed <= '1';
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p1_gain <= std_logic_vector(unsigned(p1_gain) + 1);
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end if;
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if PORT2_AUTOGAIN = '1' and p2_max > AUTOGAIN_MAX and p2_gain /= "0000" then
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-- signal too high, reduce gain
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autogain_changed <= '1';
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p2_gain <= std_logic_vector(unsigned(p2_gain) - 1);
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elsif PORT2_AUTOGAIN = '1' and p2_max < AUTOGAIN_MIN and p2_gain /= "1000" then
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-- signal too low, increase gain
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autogain_changed <= '1';
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p2_gain <= std_logic_vector(unsigned(p2_gain) + 1);
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end if;
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end if;
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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@ -209,6 +268,13 @@ begin
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mult_b(15 downto 0) <= cosine;
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mult_c <= p2_I;
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state <= P2Q;
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if autogain_changed = '1' then
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-- reset autogain memory and restart sampling process
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p1_max <= 0;
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p2_max <= 0;
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samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
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state <= Sampling;
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end if;
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when P2Q =>
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ACTIVE <= '1';
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DONE <= '0';
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@ -291,6 +357,7 @@ begin
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PORT2_Q <= p2_Q;
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REF_I <= r_I;
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REF_Q <= r_Q;
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USEDGAIN <= "00000000" & p2_gain & p1_gain;
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state <= Idle;
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end case;
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end if;
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|||
111
FPGA/VNA/Test_MAX9939.vhd
Normal file
111
FPGA/VNA/Test_MAX9939.vhd
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 21:19:15 05/29/2021
|
||||
-- Design Name:
|
||||
-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_MAX9939.vhd
|
||||
-- Project Name: VNA
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- VHDL Test Bench Created by ISE for module: MAX9939
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
-- Notes:
|
||||
-- This testbench has been automatically generated using types std_logic and
|
||||
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
|
||||
-- that these types always be used for the top-level I/O of a design in order
|
||||
-- to guarantee that the testbench will bind correctly to the post-implementation
|
||||
-- simulation model.
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY Test_MAX9939 IS
|
||||
END Test_MAX9939;
|
||||
|
||||
ARCHITECTURE behavior OF Test_MAX9939 IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
|
||||
COMPONENT MAX9939
|
||||
GENERIC(CLK_DIV : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
GAIN : IN std_logic_vector(3 downto 0);
|
||||
READY : OUT std_logic;
|
||||
CS : OUT std_logic;
|
||||
SCLK : OUT std_logic;
|
||||
DIN : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
--Inputs
|
||||
signal CLK : std_logic := '0';
|
||||
signal RESET : std_logic := '1';
|
||||
signal GAIN : std_logic_vector(3 downto 0) := (others => '0');
|
||||
|
||||
--Outputs
|
||||
signal READY : std_logic;
|
||||
signal CS : std_logic;
|
||||
signal SCLK : std_logic;
|
||||
signal DIN : std_logic;
|
||||
|
||||
-- Clock period definitions
|
||||
constant CLK_period : time := 10 ns;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: MAX9939
|
||||
GENERIC MAP(CLK_DIV => 10)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
RESET => RESET,
|
||||
GAIN => GAIN,
|
||||
READY => READY,
|
||||
CS => CS,
|
||||
SCLK => SCLK,
|
||||
DIN => DIN
|
||||
);
|
||||
|
||||
-- Clock process definitions
|
||||
CLK_process :process
|
||||
begin
|
||||
CLK <= '0';
|
||||
wait for CLK_period/2;
|
||||
CLK <= '1';
|
||||
wait for CLK_period/2;
|
||||
end process;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
stim_proc: process
|
||||
begin
|
||||
-- hold reset state for 100 ns.
|
||||
wait for 100 ns;
|
||||
RESET <= '0';
|
||||
|
||||
wait for CLK_period*10;
|
||||
|
||||
-- insert stimulus here
|
||||
wait for CLK_period*200;
|
||||
GAIN <= "1010";
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
END;
|
||||
|
|
@ -24,6 +24,7 @@
|
|||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="DFT.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MAX2871.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MAX9939.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MCP33131.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="ResetDelay.vhi"/>
|
||||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SPICommands.vhi"/>
|
||||
|
|
@ -41,6 +42,9 @@
|
|||
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MAX9939_beh.prj"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX9939_isim_beh.exe"/>
|
||||
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MAX9939_isim_beh.wdb"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
|
||||
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
|
||||
|
|
@ -135,7 +139,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764195" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604764195">
|
||||
<transform xil_pn:end_ts="1622316265" xil_pn:in_ck="-3405005612254819215" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1622316265">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
|
|
@ -144,6 +148,7 @@
|
|||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="DFT.vhd"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MAX9939.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="ResetDelay.vhd"/>
|
||||
<outfile xil_pn:name="SPIConfig.vhd"/>
|
||||
|
|
@ -152,6 +157,7 @@
|
|||
<outfile xil_pn:name="Synchronizer.vhd"/>
|
||||
<outfile xil_pn:name="Test_DFT.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX9939.vhd"/>
|
||||
<outfile xil_pn:name="Test_MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="Test_PLL.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPI.vhd"/>
|
||||
|
|
@ -165,56 +171,91 @@
|
|||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764128" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3044368668303368987" xil_pn:start_ts="1604764128">
|
||||
<transform xil_pn:end_ts="1622316001" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="2199970647637642169" xil_pn:start_ts="1622316001">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764128" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7898843873652552295" xil_pn:start_ts="1604764128">
|
||||
<transform xil_pn:end_ts="1622316001" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-4636422188803427785" xil_pn:start_ts="1622316001">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604763670" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604763670">
|
||||
<transform xil_pn:end_ts="1622315953" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622315953">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764195" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604764195">
|
||||
<transform xil_pn:end_ts="1622316265" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1622316265">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="DFT.vhd"/>
|
||||
<outfile xil_pn:name="MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="MAX9939.vhd"/>
|
||||
<outfile xil_pn:name="MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="ResetDelay.vhd"/>
|
||||
<outfile xil_pn:name="SPIConfig.vhd"/>
|
||||
<outfile xil_pn:name="Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Sweep.vhd"/>
|
||||
<outfile xil_pn:name="Synchronizer.vhd"/>
|
||||
<outfile xil_pn:name="Test_DFT.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX2871.vhd"/>
|
||||
<outfile xil_pn:name="Test_MAX9939.vhd"/>
|
||||
<outfile xil_pn:name="Test_MCP33131.vhd"/>
|
||||
<outfile xil_pn:name="Test_PLL.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPI.vhd"/>
|
||||
<outfile xil_pn:name="Test_SPICommands.vhd"/>
|
||||
<outfile xil_pn:name="Test_Sampling.vhd"/>
|
||||
<outfile xil_pn:name="Test_SinCos.vhd"/>
|
||||
<outfile xil_pn:name="Test_Window.vhd"/>
|
||||
<outfile xil_pn:name="Test_Windowing.vhd"/>
|
||||
<outfile xil_pn:name="Windowing.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
|
||||
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
|
||||
<outfile xil_pn:name="spi_slave.vhd"/>
|
||||
<outfile xil_pn:name="top.vhd"/>
|
||||
<outfile xil_pn:name="window.vhd"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764196" xil_pn:in_ck="4954137158046299803" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3520630626282717961" xil_pn:start_ts="1604764195">
|
||||
<transform xil_pn:end_ts="1622316267" xil_pn:in_ck="4459596832003765746" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="2853946142157696338" xil_pn:start_ts="1622316265">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputAdded"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="Test_MAX9939_beh.prj"/>
|
||||
<outfile xil_pn:name="Test_MAX9939_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764196" xil_pn:in_ck="-6978407093755538946" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8357625476205656394" xil_pn:start_ts="1604764196">
|
||||
<transform xil_pn:end_ts="1622316267" xil_pn:in_ck="-814711369959840581" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="8409166109357667967" xil_pn:start_ts="1622316267">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="Test_MAX9939_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
|
|
@ -224,7 +265,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764706" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604764706">
|
||||
<transform xil_pn:end_ts="1622319909" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1622319909">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
|
||||
|
|
@ -253,7 +294,7 @@
|
|||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764767" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1604764742">
|
||||
<transform xil_pn:end_ts="1622320794" xil_pn:in_ck="-4611116386143726578" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1622320769">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -271,11 +312,11 @@
|
|||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604691275" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1604691275">
|
||||
<transform xil_pn:end_ts="1622320947" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1622320947">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764774" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1604764767">
|
||||
<transform xil_pn:end_ts="1622320954" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1622320947">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
|
|
@ -284,7 +325,7 @@
|
|||
<outfile xil_pn:name="top.ngd"/>
|
||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764932" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1604764774">
|
||||
<transform xil_pn:end_ts="1622321048" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1622320954">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -300,7 +341,7 @@
|
|||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764964" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1604764932">
|
||||
<transform xil_pn:end_ts="1622321079" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1622321048">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
|
|
@ -314,7 +355,7 @@
|
|||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764980" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1604764964">
|
||||
<transform xil_pn:end_ts="1622321094" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1622321079">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
|
|
@ -368,7 +409,7 @@
|
|||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1604764964" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1604764957">
|
||||
<transform xil_pn:end_ts="1622321079" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1622321072">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
<files>
|
||||
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
|
||||
</file>
|
||||
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
|
|
@ -34,11 +34,11 @@
|
|||
</file>
|
||||
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
|
@ -68,7 +68,7 @@
|
|||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
|
@ -109,7 +109,7 @@
|
|||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
|
||||
|
|
@ -120,7 +120,7 @@
|
|||
</file>
|
||||
<file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
|
|
@ -146,6 +146,16 @@
|
|||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="176"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
|
||||
</file>
|
||||
<file xil_pn:name="MAX9939.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MAX9939.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="165"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="165"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="165"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
|
|
@ -405,8 +415,8 @@
|
|||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_DFT" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top/SA_DFT" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.DFT" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
|
|
@ -424,7 +434,7 @@
|
|||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.DFT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
|
|
@ -476,7 +486,7 @@
|
|||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|window|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MAX9939|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
|
|
|||
269
FPGA/VNA/ipcore_dir/DFT_CLK.xco
Normal file
269
FPGA/VNA/ipcore_dir/DFT_CLK.xco
Normal file
|
|
@ -0,0 +1,269 @@
|
|||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Mon Mar 15 20:29:12 2021
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# This file contains the customisation parameters for a
|
||||
# Xilinx CORE Generator IP GUI. It is strongly recommended
|
||||
# that you do not manually alter this file as it may cause
|
||||
# unexpected and unsupported behavior.
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# Generated from component: xilinx.com:ip:clk_wiz:3.6
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
# BEGIN Project Options
|
||||
SET addpads = false
|
||||
SET asysymbol = true
|
||||
SET busformat = BusFormatAngleBracketNotRipped
|
||||
SET createndf = false
|
||||
SET designentry = VHDL
|
||||
SET device = xc6slx9
|
||||
SET devicefamily = spartan6
|
||||
SET flowvendor = Other
|
||||
SET formalverification = false
|
||||
SET foundationsym = false
|
||||
SET implementationfiletype = Ngc
|
||||
SET package = tqg144
|
||||
SET removerpms = false
|
||||
SET simulationfiles = Behavioral
|
||||
SET speedgrade = -2
|
||||
SET verilogsim = false
|
||||
SET vhdlsim = true
|
||||
# END Project Options
|
||||
# BEGIN Select
|
||||
SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
|
||||
# END Select
|
||||
# BEGIN Parameters
|
||||
CSET calc_done=DONE
|
||||
CSET clk_in_sel_port=CLK_IN_SEL
|
||||
CSET clk_out1_port=CLK_OUT1
|
||||
CSET clk_out1_use_fine_ps_gui=false
|
||||
CSET clk_out2_port=CLK_OUT2
|
||||
CSET clk_out2_use_fine_ps_gui=false
|
||||
CSET clk_out3_port=CLK_OUT3
|
||||
CSET clk_out3_use_fine_ps_gui=false
|
||||
CSET clk_out4_port=CLK_OUT4
|
||||
CSET clk_out4_use_fine_ps_gui=false
|
||||
CSET clk_out5_port=CLK_OUT5
|
||||
CSET clk_out5_use_fine_ps_gui=false
|
||||
CSET clk_out6_port=CLK_OUT6
|
||||
CSET clk_out6_use_fine_ps_gui=false
|
||||
CSET clk_out7_port=CLK_OUT7
|
||||
CSET clk_out7_use_fine_ps_gui=false
|
||||
CSET clk_valid_port=CLK_VALID
|
||||
CSET clkfb_in_n_port=CLKFB_IN_N
|
||||
CSET clkfb_in_p_port=CLKFB_IN_P
|
||||
CSET clkfb_in_port=CLKFB_IN
|
||||
CSET clkfb_in_signaling=SINGLE
|
||||
CSET clkfb_out_n_port=CLKFB_OUT_N
|
||||
CSET clkfb_out_p_port=CLKFB_OUT_P
|
||||
CSET clkfb_out_port=CLKFB_OUT
|
||||
CSET clkfb_stopped_port=CLKFB_STOPPED
|
||||
CSET clkin1_jitter_ps=625.0
|
||||
CSET clkin1_ui_jitter=0.010
|
||||
CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.000
|
||||
CSET clkout1_requested_out_freq=160
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.000
|
||||
CSET clkout2_requested_out_freq=100.000
|
||||
CSET clkout2_requested_phase=0.000
|
||||
CSET clkout2_used=false
|
||||
CSET clkout3_drives=BUFG
|
||||
CSET clkout3_requested_duty_cycle=50.000
|
||||
CSET clkout3_requested_out_freq=100.000
|
||||
CSET clkout3_requested_phase=0.000
|
||||
CSET clkout3_used=false
|
||||
CSET clkout4_drives=BUFG
|
||||
CSET clkout4_requested_duty_cycle=50.000
|
||||
CSET clkout4_requested_out_freq=100.000
|
||||
CSET clkout4_requested_phase=0.000
|
||||
CSET clkout4_used=false
|
||||
CSET clkout5_drives=BUFG
|
||||
CSET clkout5_requested_duty_cycle=50.000
|
||||
CSET clkout5_requested_out_freq=100.000
|
||||
CSET clkout5_requested_phase=0.000
|
||||
CSET clkout5_used=false
|
||||
CSET clkout6_drives=BUFG
|
||||
CSET clkout6_requested_duty_cycle=50.000
|
||||
CSET clkout6_requested_out_freq=100.000
|
||||
CSET clkout6_requested_phase=0.000
|
||||
CSET clkout6_used=false
|
||||
CSET clkout7_drives=BUFG
|
||||
CSET clkout7_requested_duty_cycle=50.000
|
||||
CSET clkout7_requested_out_freq=100.000
|
||||
CSET clkout7_requested_phase=0.000
|
||||
CSET clkout7_used=false
|
||||
CSET clock_mgr_type=AUTO
|
||||
CSET component_name=DFT_CLK
|
||||
CSET daddr_port=DADDR
|
||||
CSET dclk_port=DCLK
|
||||
CSET dcm_clk_feedback=1X
|
||||
CSET dcm_clk_out1_port=CLKFX
|
||||
CSET dcm_clk_out2_port=CLK0
|
||||
CSET dcm_clk_out3_port=CLK0
|
||||
CSET dcm_clk_out4_port=CLK0
|
||||
CSET dcm_clk_out5_port=CLK0
|
||||
CSET dcm_clk_out6_port=CLK0
|
||||
CSET dcm_clkdv_divide=2.0
|
||||
CSET dcm_clkfx_divide=1
|
||||
CSET dcm_clkfx_multiply=10
|
||||
CSET dcm_clkgen_clk_out1_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out2_port=CLKFX
|
||||
CSET dcm_clkgen_clk_out3_port=CLKFX
|
||||
CSET dcm_clkgen_clkfx_divide=1
|
||||
CSET dcm_clkgen_clkfx_md_max=0.000
|
||||
CSET dcm_clkgen_clkfx_multiply=4
|
||||
CSET dcm_clkgen_clkfxdv_divide=2
|
||||
CSET dcm_clkgen_clkin_period=10.000
|
||||
CSET dcm_clkgen_notes=None
|
||||
CSET dcm_clkgen_spread_spectrum=NONE
|
||||
CSET dcm_clkgen_startup_wait=false
|
||||
CSET dcm_clkin_divide_by_2=false
|
||||
CSET dcm_clkin_period=62.500
|
||||
CSET dcm_clkout_phase_shift=NONE
|
||||
CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
|
||||
CSET dcm_notes=None
|
||||
CSET dcm_phase_shift=0
|
||||
CSET dcm_pll_cascade=NONE
|
||||
CSET dcm_startup_wait=false
|
||||
CSET den_port=DEN
|
||||
CSET din_port=DIN
|
||||
CSET dout_port=DOUT
|
||||
CSET drdy_port=DRDY
|
||||
CSET dwe_port=DWE
|
||||
CSET feedback_source=FDBK_AUTO
|
||||
CSET in_freq_units=Units_MHz
|
||||
CSET in_jitter_units=Units_UI
|
||||
CSET input_clk_stopped_port=INPUT_CLK_STOPPED
|
||||
CSET jitter_options=UI
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=4.000
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=10.000
|
||||
CSET mmcm_clkin2_period=10.000
|
||||
CSET mmcm_clkout0_divide_f=4.000
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=1
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
CSET mmcm_clkout2_divide=1
|
||||
CSET mmcm_clkout2_duty_cycle=0.500
|
||||
CSET mmcm_clkout2_phase=0.000
|
||||
CSET mmcm_clkout2_use_fine_ps=false
|
||||
CSET mmcm_clkout3_divide=1
|
||||
CSET mmcm_clkout3_duty_cycle=0.500
|
||||
CSET mmcm_clkout3_phase=0.000
|
||||
CSET mmcm_clkout3_use_fine_ps=false
|
||||
CSET mmcm_clkout4_cascade=false
|
||||
CSET mmcm_clkout4_divide=1
|
||||
CSET mmcm_clkout4_duty_cycle=0.500
|
||||
CSET mmcm_clkout4_phase=0.000
|
||||
CSET mmcm_clkout4_use_fine_ps=false
|
||||
CSET mmcm_clkout5_divide=1
|
||||
CSET mmcm_clkout5_duty_cycle=0.500
|
||||
CSET mmcm_clkout5_phase=0.000
|
||||
CSET mmcm_clkout5_use_fine_ps=false
|
||||
CSET mmcm_clkout6_divide=1
|
||||
CSET mmcm_clkout6_duty_cycle=0.500
|
||||
CSET mmcm_clkout6_phase=0.000
|
||||
CSET mmcm_clkout6_use_fine_ps=false
|
||||
CSET mmcm_clock_hold=false
|
||||
CSET mmcm_compensation=ZHOLD
|
||||
CSET mmcm_divclk_divide=1
|
||||
CSET mmcm_notes=None
|
||||
CSET mmcm_ref_jitter1=0.010
|
||||
CSET mmcm_ref_jitter2=0.010
|
||||
CSET mmcm_startup_wait=false
|
||||
CSET num_out_clks=1
|
||||
CSET override_dcm=false
|
||||
CSET override_dcm_clkgen=false
|
||||
CSET override_mmcm=false
|
||||
CSET override_pll=false
|
||||
CSET platform=lin64
|
||||
CSET pll_bandwidth=OPTIMIZED
|
||||
CSET pll_clk_feedback=CLKFBOUT
|
||||
CSET pll_clkfbout_mult=49
|
||||
CSET pll_clkfbout_phase=0.000
|
||||
CSET pll_clkin_period=9.803
|
||||
CSET pll_clkout0_divide=5
|
||||
CSET pll_clkout0_duty_cycle=0.500
|
||||
CSET pll_clkout0_phase=0.000
|
||||
CSET pll_clkout1_divide=1
|
||||
CSET pll_clkout1_duty_cycle=0.500
|
||||
CSET pll_clkout1_phase=0.000
|
||||
CSET pll_clkout2_divide=1
|
||||
CSET pll_clkout2_duty_cycle=0.500
|
||||
CSET pll_clkout2_phase=0.000
|
||||
CSET pll_clkout3_divide=1
|
||||
CSET pll_clkout3_duty_cycle=0.500
|
||||
CSET pll_clkout3_phase=0.000
|
||||
CSET pll_clkout4_divide=1
|
||||
CSET pll_clkout4_duty_cycle=0.500
|
||||
CSET pll_clkout4_phase=0.000
|
||||
CSET pll_clkout5_divide=1
|
||||
CSET pll_clkout5_duty_cycle=0.500
|
||||
CSET pll_clkout5_phase=0.000
|
||||
CSET pll_compensation=SYSTEM_SYNCHRONOUS
|
||||
CSET pll_divclk_divide=5
|
||||
CSET pll_notes=None
|
||||
CSET pll_ref_jitter=0.010
|
||||
CSET power_down_port=POWER_DOWN
|
||||
CSET prim_in_freq=16
|
||||
CSET prim_in_jitter=0.010
|
||||
CSET prim_source=No_buffer
|
||||
CSET primary_port=CLK_IN1
|
||||
CSET primitive=MMCM
|
||||
CSET primtype_sel=PLL_BASE
|
||||
CSET psclk_port=PSCLK
|
||||
CSET psdone_port=PSDONE
|
||||
CSET psen_port=PSEN
|
||||
CSET psincdec_port=PSINCDEC
|
||||
CSET relative_inclk=REL_PRIMARY
|
||||
CSET reset_port=RESET
|
||||
CSET secondary_in_freq=100.000
|
||||
CSET secondary_in_jitter=0.010
|
||||
CSET secondary_port=CLK_IN2
|
||||
CSET secondary_source=Single_ended_clock_capable_pin
|
||||
CSET ss_mod_freq=250
|
||||
CSET ss_mode=CENTER_HIGH
|
||||
CSET status_port=STATUS
|
||||
CSET summary_strings=empty
|
||||
CSET use_clk_valid=false
|
||||
CSET use_clkfb_stopped=false
|
||||
CSET use_dyn_phase_shift=false
|
||||
CSET use_dyn_reconfig=false
|
||||
CSET use_freeze=false
|
||||
CSET use_freq_synth=true
|
||||
CSET use_inclk_stopped=false
|
||||
CSET use_inclk_switchover=false
|
||||
CSET use_locked=true
|
||||
CSET use_max_i_jitter=false
|
||||
CSET use_min_o_jitter=false
|
||||
CSET use_min_power=false
|
||||
CSET use_phase_alignment=true
|
||||
CSET use_power_down=false
|
||||
CSET use_reset=true
|
||||
CSET use_spread_spectrum=false
|
||||
CSET use_spread_spectrum_1=false
|
||||
CSET use_status=false
|
||||
# END Parameters
|
||||
# BEGIN Extra information
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: fd8e1b4c
|
||||
403
FPGA/VNA/ipcore_dir/DFT_CLK.xise
Normal file
403
FPGA/VNA/ipcore_dir/DFT_CLK.xise
Normal file
|
|
@ -0,0 +1,403 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="DFT_CLK.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="DFT_CLK.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DFT_CLK|xilinx" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="DFT_CLK.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DFT_CLK" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="DFT_CLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="DFT_CLK_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="DFT_CLK_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="DFT_CLK_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="DFT_CLK_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="DFT_CLK" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2021-03-15T21:29:29" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E6495DF7B3B5170C8DE96676C882ABA7" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/DFT_CLK" xil_pn:name="DFT_CLK.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
|
|
@ -17,11 +17,11 @@
|
|||
<files>
|
||||
<file xil_pn:name="result_bram.ngc" xil_pn:type="FILE_NGC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="result_bram.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
|
|
@ -29,357 +29,28 @@
|
|||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|result_bram|result_bram_a" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="result_bram.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/result_bram" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="result_bram" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="result_bram_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="result_bram_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="result_bram_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="result_bram_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="result_bram" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-07T16:57:27" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B5404264344E1435540FD7484D40A487" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
|
|
|
|||
BIN
FPGA/VNA/top.bin
BIN
FPGA/VNA/top.bin
Binary file not shown.
|
|
@ -62,6 +62,20 @@ NET "PORT1_SCLK" SLEW = FAST;
|
|||
NET "PORT2_SCLK" SLEW = FAST;
|
||||
NET "REF_SCLK" SLEW = FAST;
|
||||
|
||||
NET "P1_PGA_CS" IOSTANDARD = LVCMOS33;
|
||||
NET "P1_PGA_SCLK" IOSTANDARD = LVCMOS33;
|
||||
NET "P1_PGA_DIN" IOSTANDARD = LVCMOS33;
|
||||
NET "P2_PGA_CS" IOSTANDARD = LVCMOS33;
|
||||
NET "P2_PGA_SCLK" IOSTANDARD = LVCMOS33;
|
||||
NET "P2_PGA_DIN" IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "P1_PGA_CS" LOC = P134;
|
||||
NET "P1_PGA_SCLK" LOC = P133;
|
||||
NET "P1_PGA_DIN" LOC = P132;
|
||||
NET "P2_PGA_CS" LOC = P131;
|
||||
NET "P2_PGA_SCLK" LOC = P127;
|
||||
NET "P2_PGA_DIN" LOC = P126;
|
||||
|
||||
NET "ATTENUATION[6]" LOC = P9;
|
||||
NET "ATTENUATION[5]" LOC = P10;
|
||||
NET "ATTENUATION[4]" LOC = P11;
|
||||
|
|
|
|||
|
|
@ -81,7 +81,13 @@ entity top is
|
|||
SOURCE_CE : out STD_LOGIC;
|
||||
REF_CONVSTART : out STD_LOGIC;
|
||||
REF_SDO : in STD_LOGIC;
|
||||
REF_SCLK : out STD_LOGIC);
|
||||
REF_SCLK : out STD_LOGIC;
|
||||
P1_PGA_CS : out STD_LOGIC;
|
||||
P1_PGA_SCLK : out STD_LOGIC;
|
||||
P1_PGA_DIN : out STD_LOGIC;
|
||||
P2_PGA_CS : out STD_LOGIC;
|
||||
P2_PGA_SCLK : out STD_LOGIC;
|
||||
P2_PGA_DIN : out STD_LOGIC);
|
||||
end top;
|
||||
|
||||
architecture Behavioral of top is
|
||||
|
|
@ -164,7 +170,10 @@ architecture Behavioral of top is
|
|||
END COMPONENT;
|
||||
|
||||
COMPONENT Sampling
|
||||
Generic(CLK_CYCLES_PRE_DONE : integer);
|
||||
Generic(CLK_CYCLES_PRE_DONE : integer;
|
||||
AUTOGAIN_SAMPLES : integer;
|
||||
AUTOGAIN_MAX : integer;
|
||||
AUTOGAIN_MIN : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
|
|
@ -179,13 +188,20 @@ architecture Behavioral of top is
|
|||
ADC_START : OUT std_logic;
|
||||
DONE : OUT std_logic;
|
||||
PRE_DONE : OUT std_logic;
|
||||
USEDGAIN : out STD_LOGIC_VECTOR (15 downto 0);
|
||||
PORT1_I : OUT std_logic_vector(47 downto 0);
|
||||
PORT1_Q : OUT std_logic_vector(47 downto 0);
|
||||
PORT2_I : OUT std_logic_vector(47 downto 0);
|
||||
PORT2_Q : OUT std_logic_vector(47 downto 0);
|
||||
REF_I : OUT std_logic_vector(47 downto 0);
|
||||
REF_Q : OUT std_logic_vector(47 downto 0);
|
||||
ACTIVE : OUT std_logic
|
||||
ACTIVE : OUT std_logic;
|
||||
PORT1_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
PORT1_GAIN_READY : in STD_LOGIC;
|
||||
PORT1_AUTOGAIN : in STD_LOGIC;
|
||||
PORT2_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
|
||||
PORT2_GAIN_READY : in STD_LOGIC;
|
||||
PORT2_AUTOGAIN : in STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT MCP33131
|
||||
|
|
@ -205,6 +221,18 @@ architecture Behavioral of top is
|
|||
SCLK : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT MAX9939
|
||||
Generic(CLK_DIV : integer);
|
||||
PORT(
|
||||
CLK : IN std_logic;
|
||||
RESET : IN std_logic;
|
||||
GAIN : IN std_logic_vector(3 downto 0);
|
||||
READY : OUT std_logic;
|
||||
CS : OUT std_logic;
|
||||
SCLK : OUT std_logic;
|
||||
DIN : OUT std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
COMPONENT MAX2871
|
||||
Generic (CLK_DIV : integer);
|
||||
PORT(
|
||||
|
|
@ -229,7 +257,7 @@ architecture Behavioral of top is
|
|||
MOSI : IN std_logic;
|
||||
NSS : IN std_logic;
|
||||
NEW_SAMPLING_DATA : IN std_logic;
|
||||
SAMPLING_RESULT : IN std_logic_vector(303 downto 0);
|
||||
SAMPLING_RESULT : IN std_logic_vector(319 downto 0);
|
||||
ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
|
||||
SOURCE_UNLOCKED : IN std_logic;
|
||||
LO_UNLOCKED : IN std_logic;
|
||||
|
|
@ -268,6 +296,10 @@ architecture Behavioral of top is
|
|||
DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
|
||||
DFT_NEXT_OUTPUT : out STD_LOGIC;
|
||||
DFT_ENABLE : out STD_LOGIC;
|
||||
PORT1_GAIN : out STD_LOGIC_VECTOR(3 downto 0);
|
||||
PORT2_GAIN : out STD_LOGIC_VECTOR(3 downto 0);
|
||||
PORT1_AUTOGAIN : out STD_LOGIC;
|
||||
PORT2_AUTOGAIN : out STD_LOGIC;
|
||||
DEBUG_STATUS : in STD_LOGIC_VECTOR (10 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
|
@ -353,7 +385,7 @@ architecture Behavioral of top is
|
|||
signal sampling_start : std_logic;
|
||||
signal sampling_samples : std_logic_vector(12 downto 0);
|
||||
signal sampling_user_samples : std_logic_vector(12 downto 0);
|
||||
signal sampling_result : std_logic_vector(303 downto 0);
|
||||
signal sampling_result : std_logic_vector(319 downto 0);
|
||||
signal sampling_window : std_logic_vector(1 downto 0);
|
||||
signal sampling_prescaler : std_logic_vector(7 downto 0);
|
||||
signal sampling_phaseinc : std_logic_vector(11 downto 0);
|
||||
|
|
@ -419,6 +451,18 @@ architecture Behavioral of top is
|
|||
signal dft_next_output : std_logic;
|
||||
signal dft_enable : std_logic;
|
||||
signal dft_reset : std_logic;
|
||||
|
||||
-- autogain signals
|
||||
signal p1_autogain_enable : std_logic;
|
||||
signal p2_autogain_enable : std_logic;
|
||||
signal p1_gain_ready : std_logic;
|
||||
signal p2_gain_ready : std_logic;
|
||||
signal p1_gain_auto : std_logic_vector (3 downto 0);
|
||||
signal p2_gain_auto : std_logic_vector (3 downto 0);
|
||||
signal p1_gain_manual : std_logic_vector (3 downto 0);
|
||||
signal p2_gain_manual : std_logic_vector (3 downto 0);
|
||||
signal p1_gain : std_logic_vector (3 downto 0);
|
||||
signal p2_gain : std_logic_vector (3 downto 0);
|
||||
begin
|
||||
|
||||
-- Reference CLK LED
|
||||
|
|
@ -562,6 +606,17 @@ begin
|
|||
CONVSTART => PORT1_CONVSTART,
|
||||
SCLK => PORT1_SCLK
|
||||
);
|
||||
Port1PGA: MAX9939
|
||||
GENERIC MAP(CLK_DIV => 21)
|
||||
PORT MAP(
|
||||
CLK => clk160,
|
||||
RESET => int_reset,
|
||||
GAIN => p1_gain,
|
||||
READY => p1_gain_ready,
|
||||
CS => P1_PGA_CS,
|
||||
SCLK => P1_PGA_SCLK,
|
||||
DIN => P1_PGA_DIN
|
||||
);
|
||||
Port2ADC: MCP33131
|
||||
GENERIC MAP(CLK_DIV => 2,
|
||||
CONVCYCLES => 77)
|
||||
|
|
@ -578,6 +633,17 @@ begin
|
|||
CONVSTART => PORT2_CONVSTART,
|
||||
SCLK => PORT2_SCLK
|
||||
);
|
||||
Port2PGA: MAX9939
|
||||
GENERIC MAP(CLK_DIV => 21)
|
||||
PORT MAP(
|
||||
CLK => clk160,
|
||||
RESET => int_reset,
|
||||
GAIN => p2_gain,
|
||||
READY => p2_gain_ready,
|
||||
CS => P2_PGA_CS,
|
||||
SCLK => P2_PGA_SCLK,
|
||||
DIN => P2_PGA_DIN
|
||||
);
|
||||
RefADC: MCP33131
|
||||
GENERIC MAP(CLK_DIV => 2,
|
||||
CONVCYCLES => 77)
|
||||
|
|
@ -612,7 +678,10 @@ begin
|
|||
);
|
||||
|
||||
Sampler: Sampling
|
||||
GENERIC MAP(CLK_CYCLES_PRE_DONE => 0)
|
||||
GENERIC MAP(CLK_CYCLES_PRE_DONE => 0,
|
||||
AUTOGAIN_SAMPLES => 16,
|
||||
AUTOGAIN_MIN => 7000,
|
||||
AUTOGAIN_MAX => 140000)
|
||||
PORT MAP(
|
||||
CLK => clk160,
|
||||
RESET => sweep_reset,
|
||||
|
|
@ -625,6 +694,7 @@ begin
|
|||
NEW_SAMPLE => windowing_ready,
|
||||
DONE => sampling_done,
|
||||
PRE_DONE => open,
|
||||
USEDGAIN => sampling_result(319 downto 304),
|
||||
START => sampling_start,
|
||||
SAMPLES => sampling_samples,
|
||||
PORT1_I => sampling_result(287 downto 240),
|
||||
|
|
@ -633,10 +703,20 @@ begin
|
|||
PORT2_Q => sampling_result(143 downto 96),
|
||||
REF_I => sampling_result(95 downto 48),
|
||||
REF_Q => sampling_result(47 downto 0),
|
||||
ACTIVE => sampling_busy
|
||||
ACTIVE => sampling_busy,
|
||||
PORT1_GAIN => p1_gain_auto,
|
||||
PORT1_GAIN_READY => p1_gain_ready,
|
||||
PORT1_AUTOGAIN => p1_autogain_enable,
|
||||
PORT2_GAIN => p2_gain_auto,
|
||||
PORT2_GAIN_READY => p2_gain_ready,
|
||||
PORT2_AUTOGAIN => p2_autogain_enable
|
||||
);
|
||||
|
||||
sweep_reset <= not aux3_sync;
|
||||
|
||||
-- gain selection
|
||||
p1_gain <= p1_gain_auto when p1_autogain_enable = '1' else p1_gain_manual;
|
||||
p2_gain <= p2_gain_auto when p2_autogain_enable = '1' else p2_gain_manual;
|
||||
|
||||
SweepModule: Sweep PORT MAP(
|
||||
CLK => clk160,
|
||||
|
|
@ -748,6 +828,10 @@ begin
|
|||
DFT_OUTPUT => dft_output,
|
||||
DFT_NEXT_OUTPUT => dft_next_output,
|
||||
DFT_ENABLE => dft_enable,
|
||||
PORT1_GAIN => p1_gain_manual,
|
||||
PORT2_GAIN => p2_gain_manual,
|
||||
PORT1_AUTOGAIN => p1_autogain_enable,
|
||||
PORT2_AUTOGAIN => p2_autogain_enable,
|
||||
DEBUG_STATUS => debug
|
||||
);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue