LibreVNA/FPGA/VNA/top.bin
Jan Käberich a4faeb28b0 Working dwell time feature
- Bugfixes:
	- improve SPI timing in FPGA
	- fix markers and reduce CPU load when using markers with fast traces
- New features:
	- dwell time configurable in acquisition toolbar
	- PLL settling delay in device configuration
	- device configuration persistent across power cycles
2025-01-03 14:36:10 +01:00

334 KiB