mirror of
https://github.com/jankae/LibreVNA.git
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- Bugfixes: - improve SPI timing in FPGA - fix markers and reduce CPU load when using markers with fast traces - New features: - dwell time configurable in acquisition toolbar - PLL settling delay in device configuration - device configuration persistent across power cycles |
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| .. | ||
| Generator/ipcore_dir | ||
| VNA | ||
| .gitignore | ||
| AMAttenuationCalculator.py | ||
| WindowCoefficientGenerator.py | ||