mirror of
https://github.com/jankae/LibreVNA.git
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222 lines
7.2 KiB
VHDL
222 lines
7.2 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:51:11 05/05/2020
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-- Design Name:
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-- Module Name: SPICommands - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity SPICommands is
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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SCLK : in STD_LOGIC;
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MOSI : in STD_LOGIC;
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MISO : out STD_LOGIC;
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NSS : in STD_LOGIC;
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SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
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SOURCE_POWER : out STD_LOGIC_VECTOR(1 downto 0);
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SOURCE_ATTENUATION : out STD_LOGIC_VECTOR(6 downto 0);
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SOURCE_BANDSELECT : out STD_LOGIC; -- 0: highband, 1: lowband
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SOURCE_PORTSELECT : out STD_LOGIC; -- 0: Port 1, 1: Port 2
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SOURCE_UNLOCKED : in STD_LOGIC;
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-- SOURCE VCO lookup table
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SOURCE_VCO_INDEX : out STD_LOGIC_VECTOR (5 downto 0);
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SOURCE_VCO_MAXFREQ : out STD_LOGIC_VECTOR (15 downto 0);
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SOURCE_VCO_WRITE : out STD_LOGIC;
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-- Modulation FIFO signals
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MOD_FIFO_DATA : out STD_LOGIC_VECTOR (7 downto 0);
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MOD_FIFO_WRITE : out STD_LOGIC;
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MOD_FIFO_UNDERFLOW : in STD_LOGIC;
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MOD_FIFO_OVERFLOW : in STD_LOGIC;
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MOD_FIFO_THRESHOLD_CROSSED : in STD_LOGIC;
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MOD_FIFO_THRESHOLD : out STD_LOGIC_VECTOR (10 downto 0);
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-- Modulation control signals
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MOD_ENABLE : out STD_LOGIC;
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MOD_PHASE_INC : out STD_LOGIC_VECTOR (15 downto 0);
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MOD_CENTER_FREQ : out STD_LOGIC_VECTOR (32 downto 0);
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MOD_DEVIATION_FREQ : out STD_LOGIC_VECTOR (25 downto 0);
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MOD_AM_DEPTH : out STD_LOGIC_VECTOR (6 downto 0);
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MOD_VCO_MIN : out STD_LOGIC_VECTOR (31 downto 0);
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AMP_SHDN : out STD_LOGIC;
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SOURCE_RF_EN : out STD_LOGIC;
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SOURCE_CE_EN : out STD_LOGIC;
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PORTSWITCH_EN : out STD_LOGIC;
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LEDS : out STD_LOGIC_VECTOR(2 downto 0);
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INTERRUPT_ASSERTED : out STD_LOGIC);
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end SPICommands;
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architecture Behavioral of SPICommands is
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COMPONENT spi_slave
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Generic(W : integer);
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PORT(
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SPI_CLK : in STD_LOGIC;
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MISO : out STD_LOGIC;
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MOSI : in STD_LOGIC;
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CS : in STD_LOGIC;
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BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
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BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
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CLK : in STD_LOGIC;
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COMPLETE : out STD_LOGIC
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);
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END COMPONENT;
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-- SPI control signals
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signal spi_buf_out : std_logic_vector(15 downto 0);
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signal spi_buf_in : std_logic_vector(15 downto 0);
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signal spi_complete : std_logic;
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signal word_cnt : integer range 0 to 19;
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type SPI_states is (FirstWord, WriteVCOTable, WriteModulationData, WriteRegister);
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signal state : SPI_states;
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signal selected_register : integer range 0 to 31;
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signal last_NSS : std_logic;
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signal VCO_table_write : std_logic;
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signal mod_first_byte : std_logic;
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signal mod_second_byte : std_logic;
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signal mod_data_LSB : std_logic_vector(7 downto 0);
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-- Configuration registers
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signal interrupt_mask : std_logic_vector(15 downto 0);
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signal interrupt_status : std_logic_vector(15 downto 0);
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begin
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SPI: spi_slave
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GENERIC MAP(w => 16)
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PORT MAP(
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SPI_CLK => SCLK,
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MISO => MISO,
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MOSI => MOSI,
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CS => NSS,
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BUF_OUT => spi_buf_out,
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BUF_IN => spi_buf_in,
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CLK => CLK,
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COMPLETE =>spi_complete
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);
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MOD_FIFO_WRITE <= mod_first_byte or mod_second_byte;
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SOURCE_VCO_WRITE <= VCO_table_write;
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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AMP_SHDN <= '1';
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SOURCE_RF_EN <= '0';
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SOURCE_CE_EN <= '0';
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PORTSWITCH_EN <= '0';
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LEDS <= (others => '1');
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interrupt_status <= (others => '0');
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interrupt_mask <= (others => '0');
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INTERRUPT_ASSERTED <= '0';
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last_NSS <= '1';
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MOD_ENABLE <= '0';
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else
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interrupt_status <= "00000000000" & MOD_FIFO_THRESHOLD_CROSSED & MOD_FIFO_UNDERFLOW & MOD_FIFO_OVERFLOW & SOURCE_UNLOCKED & "0";
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if (interrupt_status and interrupt_mask) = "0000000000000000" then
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INTERRUPT_ASSERTED <= '0';
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else
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INTERRUPT_ASSERTED <= '1';
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end if;
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if mod_first_byte = '1' then
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mod_first_byte <= '0';
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mod_second_byte <= '1';
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MOD_FIFO_DATA <= mod_data_LSB;
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end if;
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if mod_second_byte = '1' then
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mod_second_byte <= '0';
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end if;
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if VCO_table_write = '1' then
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VCO_table_write <= '0';
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end if;
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last_NSS <= NSS;
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if NSS = '0' and last_NSS = '1' then
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word_cnt <= 0;
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spi_buf_in <= interrupt_status;
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state <= FirstWord;
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elsif spi_complete = '1' then
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word_cnt <= word_cnt + 1;
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case state is
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when FirstWord =>
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-- initial word determines action
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case spi_buf_out(15 downto 13) is
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when "000" => state <= WriteVCOTable;
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-- also extract the point number
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SOURCE_VCO_INDEX <= spi_buf_out(5 downto 0);
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when "010" => state <= FirstWord;
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spi_buf_in <= "1111000010100101";
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when "100" => state <= WriteRegister;
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selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
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when "001" => state <= WriteModulationData;
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when others => state <= FirstWord;
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end case;
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when WriteRegister =>
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-- write received data into previously selected register
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case selected_register is
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when 0 => interrupt_mask <= spi_buf_out;
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when 1 => SOURCE_FILTER <= spi_buf_out(1 downto 0);
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SOURCE_POWER <= spi_buf_out(3 downto 2);
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SOURCE_ATTENUATION <= spi_buf_out(10 downto 4);
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SOURCE_BANDSELECT <= spi_buf_out(11);
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SOURCE_PORTSELECT <= spi_buf_out(12);
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SOURCE_CE_EN <= spi_buf_out(13);
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SOURCE_RF_EN <= spi_buf_out(14);
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AMP_SHDN <= spi_buf_out(15);
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when 2 => MOD_ENABLE <= spi_buf_out(0);
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MOD_AM_DEPTH <= spi_buf_out(7 downto 1);
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LEDS <= not spi_buf_out(15 downto 13);
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when 3 => MOD_PHASE_INC <= spi_buf_out;
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when 4 => MOD_CENTER_FREQ(15 downto 0) <= spi_buf_out;
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when 5 => MOD_CENTER_FREQ(31 downto 16) <= spi_buf_out;
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when 6 => MOD_DEVIATION_FREQ(15 downto 0) <= spi_buf_out;
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when 7 => MOD_CENTER_FREQ(32) <= spi_buf_out(15);
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MOD_DEVIATION_FREQ(25 downto 16) <= spi_buf_out(9 downto 0);
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when 8 => MOD_VCO_MIN(15 downto 0) <= spi_buf_out;
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when 9 => MOD_VCO_MIN(31 downto 16) <= spi_buf_out;
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when 10 => MOD_FIFO_THRESHOLD <= spi_buf_out(10 downto 0);
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when others =>
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end case;
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selected_register <= selected_register + 1;
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when WriteVCOTable =>
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SOURCE_VCO_MAXFREQ <= spi_buf_out;
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VCO_table_write <= '1';
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when WriteModulationData =>
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-- add two new bytes to the modulation data
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MOD_FIFO_DATA <= spi_buf_out(15 downto 8);
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mod_first_byte <= '1';
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mod_data_LSB <= spi_buf_out(7 downto 0);
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end case;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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