LibreVNA/FPGA/Generator
2022-06-08 17:17:15 +02:00
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ipcore_dir Generator FPGA image test bench 2022-06-08 17:17:15 +02:00
Generator.gise Generator FPGA image test bench 2022-06-08 17:17:15 +02:00
Generator.xise Generator FPGA image test bench 2022-06-08 17:17:15 +02:00
MAX2871.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
MAX2871_Calc.vhd Description of generator FPGA protocol 2022-06-08 13:32:49 +02:00
Modulator.vhd Description of generator FPGA protocol 2022-06-08 13:32:49 +02:00
RationalApproximation.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
ResetDelay.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
spi_slave.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
SPIConfig.vhd Generator FPGA image test bench 2022-06-08 17:17:15 +02:00
Synchronizer.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
Test_Generator.vhd Generator FPGA image test bench 2022-06-08 17:17:15 +02:00
Test_MAX2871.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
test_modulator.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
Test_PLL.vhd Generator FPGA image test bench 2022-06-08 17:17:15 +02:00
Test_RationalApproximation.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
Test_SinCos.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
Test_SPI.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
Test_SPICommands.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
Test_Window.vhd Untested generator FPGA image 2022-06-08 02:06:08 +02:00
top.bin Description of generator FPGA protocol 2022-06-08 13:32:49 +02:00
top.ucf Untested generator FPGA image 2022-06-08 02:06:08 +02:00
top.vhd Description of generator FPGA protocol 2022-06-08 13:32:49 +02:00