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Generator FPGA image test bench

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This commit is contained in:
Jan Käberich 2022-06-08 17:17:15 +02:00
parent 35c2044ee5
commit 0394b52da0
8 changed files with 569 additions and 44 deletions
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4
Documentation/DeveloperInfo/FPGA_protocol_Generator.tex
View file

@ -276,9 +276,9 @@ LED num & Function\\
Determines the rate at which the modulation module consumes samples:
$$
f_{sample} = \frac{104 MHz * MOD\_PHASE\_INC}{2^{27}}
f_{sample} = \frac{102.4 MHz * MOD\_PHASE\_INC}{2^{27}}
$$
Example: set to 25811 for a sample rate of approximately 20 kHz.
Example: set to 26214 for a sample rate of approximately 20 kHz.
\subsection{Modulation center frequency LSB register: 0x04}
\label{reg:mod:center:lsb}

BIN
Documentation/DeveloperInfo/FPGA_protocol_VNA.pdf
View file

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104
FPGA/Generator/Generator.gise
View file

@ -44,6 +44,9 @@
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sweep.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Generator_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Generator_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Generator_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
@ -76,6 +79,7 @@
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
@ -142,64 +146,109 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654599019" xil_pn:in_ck="4030793588547811674" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1654599019">
<transform xil_pn:end_ts="1654700248" xil_pn:in_ck="4594151046861275780" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1654700248">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MAX2871_Calc.vhd"/>
<outfile xil_pn:name="Modulator.vhd"/>
<outfile xil_pn:name="RationalApproximation.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_Generator.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_RationalApproximation.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="test_modulator.vhd"/>
<outfile xil_pn:name="top.vhd"/>
</transform>
<transform xil_pn:end_ts="1654598846" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-4283386684047486644" xil_pn:start_ts="1654598846">
<transform xil_pn:end_ts="1654700248" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="6343328024339614396" xil_pn:start_ts="1654700248">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654598846" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6347147868262137290" xil_pn:start_ts="1654598846">
<transform xil_pn:end_ts="1654700248" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-9138947074428086470" xil_pn:start_ts="1654700248">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1654598476" xil_pn:in_ck="5973348650244128832" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1654598476">
<transform xil_pn:end_ts="1654697286" xil_pn:in_ck="8843808394389964678" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1654697286">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="ipcore_dir/AMMult.ngc"/>
<outfile xil_pn:name="ipcore_dir/AMMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SampleMemory.ngc"/>
<outfile xil_pn:name="ipcore_dir/SampleMemory.vhd"/>
<outfile xil_pn:name="ipcore_dir/VCO_Mem.ngc"/>
<outfile xil_pn:name="ipcore_dir/VCO_Mem.vhd"/>
<outfile xil_pn:name="ipcore_dir/wide_mult.ngc"/>
<outfile xil_pn:name="ipcore_dir/wide_mult.vhd"/>
</transform>
<transform xil_pn:end_ts="1654599019" xil_pn:in_ck="2548064732582717041" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1654599019">
<transform xil_pn:end_ts="1654700248" xil_pn:in_ck="1599113018014500098" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1654700248">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MAX2871_Calc.vhd"/>
<outfile xil_pn:name="Modulator.vhd"/>
<outfile xil_pn:name="RationalApproximation.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_Generator.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_RationalApproximation.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="ipcore_dir/AMMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SampleMemory.vhd"/>
<outfile xil_pn:name="ipcore_dir/VCO_Mem.vhd"/>
<outfile xil_pn:name="ipcore_dir/wide_mult.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="test_modulator.vhd"/>
<outfile xil_pn:name="top.vhd"/>
</transform>
<transform xil_pn:end_ts="1654599021" xil_pn:in_ck="-2026448475602291214" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8414461116844403576" xil_pn:start_ts="1654599019">
<transform xil_pn:end_ts="1654700250" xil_pn:in_ck="1599113018014500098" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-1155953094416498088" xil_pn:start_ts="1654700248">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="Test_Generator_beh.prj"/>
<outfile xil_pn:name="Test_Generator_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1654599021" xil_pn:in_ck="-1017121848817523979" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="2825765674452219525" xil_pn:start_ts="1654599021">
<transform xil_pn:end_ts="1654700250" xil_pn:in_ck="-2685546161606845206" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1532359730187106459" xil_pn:start_ts="1654700250">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="Test_Generator_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
<transform xil_pn:end_ts="1654646732" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1654646732">
<status xil_pn:value="SuccessfullyRun"/>
@ -242,7 +291,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top.lso"/>
@ -263,6 +314,7 @@
<transform xil_pn:end_ts="1654687642" xil_pn:in_ck="7073755081550385991" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1654687639">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="top.bld"/>
@ -273,6 +325,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="top.pcf"/>
<outfile xil_pn:name="top_map.map"/>
@ -287,6 +342,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="top.ncd"/>
<outfile xil_pn:name="top.pad"/>
@ -302,6 +358,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top.bgn"/>
<outfile xil_pn:name="top.bin"/>
@ -316,6 +373,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
@ -326,6 +384,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
@ -337,6 +396,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
@ -348,6 +408,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
@ -355,6 +416,7 @@
<transform xil_pn:end_ts="1654687656" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1654687654">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top.twr"/>
<outfile xil_pn:name="top.twx"/>

42
FPGA/Generator/Generator.xise
View file

@ -16,26 +16,26 @@
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
@ -57,7 +57,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
@ -73,7 +73,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
@ -83,7 +83,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="RationalApproximation.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ipcore_dir/wide_mult.xco" xil_pn:type="FILE_COREGEN">
@ -97,31 +97,37 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="MAX2871_Calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="ipcore_dir/VCO_Mem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="Modulator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="ipcore_dir/SampleMemory.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ipcore_dir/AMMult.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="test_modulator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="201"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="201"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="Test_Generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="166"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="166"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
@ -381,8 +387,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/test_modulator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test_modulator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_Generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -400,7 +406,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.test_modulator" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_Generator" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -452,7 +458,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|test_modulator|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Generator|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="Generator" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

1
FPGA/Generator/SPIConfig.vhd
View file

@ -137,6 +137,7 @@ begin
interrupt_mask <= (others => '0');
INTERRUPT_ASSERTED <= '0';
last_NSS <= '1';
MOD_ENABLE <= '0';
else
interrupt_status <= "00000000000" & MOD_FIFO_THRESHOLD_CROSSED & MOD_FIFO_UNDERFLOW & MOD_FIFO_OVERFLOW & SOURCE_UNLOCKED & "0";
if (interrupt_status and interrupt_mask) = "0000000000000000" then

456
FPGA/Generator/Test_Generator.vhd Normal file
View file

@ -0,0 +1,456 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:08:07 06/08/2022
-- Design Name:
-- Module Name: /home/jan/Projekte/LibreVNA/FPGA/Generator/Test_Generator.vhd
-- Project Name: Generator
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY Test_Generator IS
END Test_Generator;
ARCHITECTURE behavior OF Test_Generator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
MCU_MOSI : IN std_logic;
MCU_NSS : IN std_logic;
MCU_INTR : OUT std_logic;
MCU_SCK : IN std_logic;
MCU_MISO : OUT std_logic;
MCU_AUX1 : IN std_logic;
MCU_AUX2 : IN std_logic;
MCU_AUX3 : IN std_logic;
PORT2_CONVSTART : OUT std_logic;
PORT2_SDO : IN std_logic;
PORT2_SCLK : OUT std_logic;
PORT2_MIX2_EN : OUT std_logic;
PORT2_MIX1_EN : OUT std_logic;
PORT1_CONVSTART : OUT std_logic;
PORT1_SDO : IN std_logic;
PORT1_SCLK : OUT std_logic;
PORT1_MIX2_EN : OUT std_logic;
PORT1_MIX1_EN : OUT std_logic;
LO1_MUX : IN std_logic;
LO1_RF_EN : OUT std_logic;
LO1_LD : IN std_logic;
LO1_CLK : OUT std_logic;
LO1_MOSI : OUT std_logic;
LO1_LE : OUT std_logic;
LO1_CE : OUT std_logic;
LEDS : OUT std_logic_vector(7 downto 0);
REF_MIX2_EN : OUT std_logic;
REF_MIX1_EN : OUT std_logic;
ATTENUATION : OUT std_logic_vector(6 downto 0);
AMP_PWDN : OUT std_logic;
PORT1_SELECT : OUT std_logic;
PORT2_SELECT : OUT std_logic;
PORT_SELECT1 : OUT std_logic;
PORT_SELECT2 : OUT std_logic;
BAND_SELECT_HIGH : OUT std_logic;
BAND_SELECT_LOW : OUT std_logic;
FILT_OUT_C1 : OUT std_logic;
FILT_OUT_C2 : OUT std_logic;
FILT_IN_C1 : OUT std_logic;
FILT_IN_C2 : OUT std_logic;
SOURCE_RF_EN : OUT std_logic;
SOURCE_LD : IN std_logic;
SOURCE_MUX : IN std_logic;
SOURCE_CLK : OUT std_logic;
SOURCE_MOSI : OUT std_logic;
SOURCE_LE : OUT std_logic;
SOURCE_CE : OUT std_logic;
REF_CONVSTART : OUT std_logic;
REF_SDO : IN std_logic;
REF_SCLK : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal MCU_MOSI : std_logic := '0';
signal MCU_NSS : std_logic := '1';
signal MCU_SCK : std_logic := '0';
signal MCU_AUX1 : std_logic := '0';
signal MCU_AUX2 : std_logic := '0';
signal MCU_AUX3 : std_logic := '1';
signal PORT2_SDO : std_logic := '0';
signal PORT1_SDO : std_logic := '0';
signal LO1_MUX : std_logic := '0';
signal LO1_LD : std_logic := '1';
signal SOURCE_LD : std_logic := '1';
signal SOURCE_MUX : std_logic := '0';
signal REF_SDO : std_logic := '0';
--Outputs
signal MCU_INTR : std_logic;
signal MCU_MISO : std_logic;
signal PORT2_CONVSTART : std_logic;
signal PORT2_SCLK : std_logic;
signal PORT2_MIX2_EN : std_logic;
signal PORT2_MIX1_EN : std_logic;
signal PORT1_CONVSTART : std_logic;
signal PORT1_SCLK : std_logic;
signal PORT1_MIX2_EN : std_logic;
signal PORT1_MIX1_EN : std_logic;
signal LO1_RF_EN : std_logic;
signal LO1_CLK : std_logic;
signal LO1_MOSI : std_logic;
signal LO1_LE : std_logic;
signal LO1_CE : std_logic;
signal LEDS : std_logic_vector(7 downto 0);
signal REF_MIX2_EN : std_logic;
signal REF_MIX1_EN : std_logic;
signal ATTENUATION : std_logic_vector(6 downto 0);
signal AMP_PWDN : std_logic;
signal PORT1_SELECT : std_logic;
signal PORT2_SELECT : std_logic;
signal PORT_SELECT1 : std_logic;
signal PORT_SELECT2 : std_logic;
signal BAND_SELECT_HIGH : std_logic;
signal BAND_SELECT_LOW : std_logic;
signal FILT_OUT_C1 : std_logic;
signal FILT_OUT_C2 : std_logic;
signal FILT_IN_C1 : std_logic;
signal FILT_IN_C2 : std_logic;
signal SOURCE_RF_EN : std_logic;
signal SOURCE_CLK : std_logic;
signal SOURCE_MOSI : std_logic;
signal SOURCE_LE : std_logic;
signal SOURCE_CE : std_logic;
signal REF_CONVSTART : std_logic;
signal REF_SCLK : std_logic;
signal data_signal : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 62.5 ns;
constant SPI_CLK_period : time := 50 ns;
constant center_freq : std_logic_vector (32 downto 0) := std_logic_vector(to_unsigned(129055507, 33));
constant deviation_freq : std_logic_vector (25 downto 0) := std_logic_vector(to_unsigned(25811102, 26));
constant minimum_vco_freq : std_logic_vector (31 downto 0) := "11100110110001001110110001001111";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
CLK => CLK,
RESET => RESET,
MCU_MOSI => MCU_MOSI,
MCU_NSS => MCU_NSS,
MCU_INTR => MCU_INTR,
MCU_SCK => MCU_SCK,
MCU_MISO => MCU_MISO,
MCU_AUX1 => MCU_AUX1,
MCU_AUX2 => MCU_AUX2,
MCU_AUX3 => MCU_AUX3,
PORT2_CONVSTART => PORT2_CONVSTART,
PORT2_SDO => PORT2_SDO,
PORT2_SCLK => PORT2_SCLK,
PORT2_MIX2_EN => PORT2_MIX2_EN,
PORT2_MIX1_EN => PORT2_MIX1_EN,
PORT1_CONVSTART => PORT1_CONVSTART,
PORT1_SDO => PORT1_SDO,
PORT1_SCLK => PORT1_SCLK,
PORT1_MIX2_EN => PORT1_MIX2_EN,
PORT1_MIX1_EN => PORT1_MIX1_EN,
LO1_MUX => LO1_MUX,
LO1_RF_EN => LO1_RF_EN,
LO1_LD => LO1_LD,
LO1_CLK => LO1_CLK,
LO1_MOSI => LO1_MOSI,
LO1_LE => LO1_LE,
LO1_CE => LO1_CE,
LEDS => LEDS,
REF_MIX2_EN => REF_MIX2_EN,
REF_MIX1_EN => REF_MIX1_EN,
ATTENUATION => ATTENUATION,
AMP_PWDN => AMP_PWDN,
PORT1_SELECT => PORT1_SELECT,
PORT2_SELECT => PORT2_SELECT,
PORT_SELECT1 => PORT_SELECT1,
PORT_SELECT2 => PORT_SELECT2,
BAND_SELECT_HIGH => BAND_SELECT_HIGH,
BAND_SELECT_LOW => BAND_SELECT_LOW,
FILT_OUT_C1 => FILT_OUT_C1,
FILT_OUT_C2 => FILT_OUT_C2,
FILT_IN_C1 => FILT_IN_C1,
FILT_IN_C2 => FILT_IN_C2,
SOURCE_RF_EN => SOURCE_RF_EN,
SOURCE_LD => SOURCE_LD,
SOURCE_MUX => SOURCE_MUX,
SOURCE_CLK => SOURCE_CLK,
SOURCE_MOSI => SOURCE_MOSI,
SOURCE_LE => SOURCE_LE,
SOURCE_CE => SOURCE_CE,
REF_CONVSTART => REF_CONVSTART,
REF_SDO => REF_SDO,
REF_SCLK => REF_SCLK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure SPI(data : std_logic_vector(15 downto 0)) is
begin
MCU_MOSI <= data(15);
data_signal <= data(14 downto 0) & "0";
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
MCU_MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
MCU_SCK <= '1';
wait for SPI_CLK_period/2;
MCU_SCK <= '0';
end procedure SPI;
begin
RESET <= '1';
-- hold reset state for 100 ns.
wait for 1000 ns;
MCU_AUX3 <= '1'; -- stop modulation
RESET <= '0';
wait for CLK_period*10;
-- insert stimulus here
-- configure VCO table (only use first four entries)
-- VCO 0 is good up to 3GHz
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0000000000000000");
SPI(std_logic_vector(to_unsigned(29538, 16)));
MCU_NSS <= '1';
-- VCO 1 is good up to 4GHz
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0000000000000001");
SPI(std_logic_vector(to_unsigned(39385, 16)));
MCU_NSS <= '1';
-- VCO 2 is good up to 5GHz
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0000000000000010");
SPI(std_logic_vector(to_unsigned(49231, 16)));
MCU_NSS <= '1';
-- VCO 3 is good up to 6GHz
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0000000000000011");
SPI(std_logic_vector(to_unsigned(59077, 16)));
MCU_NSS <= '1';
-- configure modulation
-- using FM/AM combination:
-- center 100 GHz, 20 MHz deviation
-- -3dB base attenuation, 100% depth
-- set band/port/filter/base attenuation, enable PLL/AMP
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000001");
SPI("1111000110000110");
MCU_NSS <= '1';
-- set AM depth, enable modulation
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000010");
SPI("0000000011111111");
MCU_NSS <= '1';
-- set 20kHz modulation rate
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000011");
SPI(std_logic_vector(to_unsigned(26214, 16)));
MCU_NSS <= '1';
-- set center frequency
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000100");
SPI(center_freq(15 downto 0));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000101");
SPI(center_freq(31 downto 16));
MCU_NSS <= '1';
-- set deviation frequency
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000110");
SPI(deviation_freq(15 downto 0));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000000111");
SPI(center_freq(32) & "00000" & center_freq(25 downto 16));
MCU_NSS <= '1';
-- set minimum VCO frequency to 3GHz
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000001000");
SPI(minimum_vco_freq(15 downto 0));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000001001");
SPI(minimum_vco_freq(31 downto 16));
MCU_NSS <= '1';
-- set FIFO threshold to 100
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("1000000000001010");
SPI(std_logic_vector(to_unsigned(100, 16)));
MCU_NSS <= '1';
wait for CLK_period*10;
MCU_NSS <= '0';
SPI("0010000000000000");
for i in 0 to 63 loop
-- write sample FIFO
wait for CLK_period*10;
SPI(std_logic_vector(to_unsigned(i*4, 8)) & std_logic_vector(to_unsigned(i*4+2, 8)));
end loop;
MCU_NSS <= '0';
wait for CLK_period*10;
-- start the modulation
MCU_AUX3 <= '0';
wait;
end process;
END;

4
FPGA/Generator/Test_PLL.vhd
View file

@ -58,7 +58,7 @@ ARCHITECTURE behavior OF Test_PLL IS
signal LOCKED : std_logic;
-- Clock period definitions
constant CLK_IN1_period : time := 20 ns;
constant CLK_IN1_period : time := 62.5 ns;
BEGIN
@ -86,7 +86,7 @@ BEGIN
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
wait for 1000 ns;
RESET <= '0';
wait for CLK_IN1_period*10;

2
FPGA/Generator/ipcore_dir/VCO_Mem.xise
View file

@ -20,7 +20,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="VCO_Mem.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>