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master 5dafe7afa5 · update all X coordinates of math traces when start or end changes · Updated 2026-04-08 18:02:21 +00:00

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build_test 3422f0b8f6 · automatic build test · Updated 2025-11-23 18:55:31 +00:00	26 8		ZIP  TAR.GZ
prototype_testing 461d3e4e84 · add magic header value for hardware version 0xFD · Updated 2025-08-23 11:27:42 +00:00	47 10		ZIP  TAR.GZ
feature_view_save 668f050988 · WIP: save view configuration separately · Updated 2024-09-18 07:06:43 +00:00    jankae	197 1		ZIP  TAR.GZ
spike_improvement 85f431936f · merge ADC sample rate change with IF shift feature · Updated 2024-05-26 13:20:05 +00:00    jankae	214 2		ZIP  TAR.GZ
SA_phase_difference 963578cc9f · Preserve phase information in spectrum analyzer mode · Updated 2022-07-17 16:04:16 +00:00    jankae	592 1		ZIP  TAR.GZ
multiple_FPGA_images 05d6f973be · Merge branch 'master' into multiple_FPGA_images · Updated 2022-06-12 19:18:02 +00:00    jankae	666 6		ZIP  TAR.GZ
layout_6_layers f6b15537d8 · Additional shielding VIAs for LO · Updated 2022-02-22 20:44:47 +00:00    jankae	867 27		ZIP  TAR.GZ
eval_v2 ed79a1ac61 · added pdf of schematic · Updated 2022-02-11 13:35:05 +00:00    jankae	867 20		ZIP  TAR.GZ
spike_removal 5e7ab8fb3c · Shifting IF frequencies to remove spikes · Updated 2021-12-01 20:11:48 +00:00    jankae	765 1		ZIP  TAR.GZ
kicad 9e86049804 · Merge pull request #7 from bvernoux/master · Updated 2020-11-01 13:36:55 +00:00    jankae	1055 2		ZIP  TAR.GZ