CONFIG VCCAUX  = 3.3;
# Global FPGA clock
NET "CLK" PERIOD = 62.5 ns HIGH 50%;

# Constraints for SPI interface to MCU
NET "MCU_SCK" PERIOD = 23.52941176ns HIGH 50%;
NET "MCU_MOSI" OFFSET = IN 2ns VALID 3ns BEFORE "MCU_SCK";
NET "MCU_MISO" OFFSET = OUT 18.529ns VALID 10ns AFTER "MCU_SCK";
NET "MCU_MISO" SLEW = FAST;

# ADC constraints
NET "REF_SCLK" PERIOD = 19.5ns HIGH 50%;
NET "REF_SDO" OFFSET = IN 	9ns VALID 9ns BEFORE "REF_SCLK";
NET "PORT1_SCLK" PERIOD = 19.5ns HIGH 50%;
NET "PORT1_SDO" OFFSET = IN 	9ns VALID 9ns BEFORE "PORT1_SCLK";
NET "PORT2_SCLK" PERIOD = 19.5ns HIGH 50%;
NET "PORT2_SDO" OFFSET = IN 	9ns VALID 9ns BEFORE "PORT2_SCLK";
NET "PORT1_SCLK" SLEW = FAST;
NET "PORT2_SCLK" SLEW = FAST;
NET "REF_SCLK" SLEW = FAST;

NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[4]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[3]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[2]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[1]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[0]" IOSTANDARD = LVCMOS33;

NET "LEDS[7]" IOSTANDARD = LVCMOS33;
NET "LEDS[6]" IOSTANDARD = LVCMOS33;
NET "LEDS[5]" IOSTANDARD = LVCMOS33;
NET "LEDS[4]" IOSTANDARD = LVCMOS33;
NET "LEDS[3]" IOSTANDARD = LVCMOS33;
NET "LEDS[2]" IOSTANDARD = LVCMOS33;
NET "LEDS[1]" IOSTANDARD = LVCMOS33;
NET "LEDS[0]" IOSTANDARD = LVCMOS33;

NET "AMP_PWDN" IOSTANDARD = LVCMOS33;
NET "CLK" IOSTANDARD = LVCMOS33;
NET "FILT_IN_C2" IOSTANDARD = LVCMOS33;
NET "FILT_IN_C1" IOSTANDARD = LVCMOS33;
NET "FILT_OUT_C2" IOSTANDARD = LVCMOS33;
NET "FILT_OUT_C1" IOSTANDARD = LVCMOS33;
NET "LO1_CE" IOSTANDARD = LVCMOS33;
NET "LO1_LD" IOSTANDARD = LVCMOS33;
NET "LO1_LE" IOSTANDARD = LVCMOS33;
NET "LO1_CLK" IOSTANDARD = LVCMOS33;
NET "LO1_MOSI" IOSTANDARD = LVCMOS33;
NET "LO1_MUX" IOSTANDARD = LVCMOS33;
NET "MCU_AUX1" IOSTANDARD = LVCMOS33;
NET "LO1_RF_EN" IOSTANDARD = LVCMOS33;
NET "SOURCE_RF_EN" IOSTANDARD = LVCMOS33;
NET "SOURCE_MUX" IOSTANDARD = LVCMOS33;
NET "SOURCE_LE" IOSTANDARD = LVCMOS33;
NET "SOURCE_MOSI" IOSTANDARD = LVCMOS33;
NET "SOURCE_LD" IOSTANDARD = LVCMOS33;
NET "SOURCE_CLK" IOSTANDARD = LVCMOS33;
NET "SOURCE_CE" IOSTANDARD = LVCMOS33;
NET "RESET" IOSTANDARD = LVCMOS33;
NET "REF_SDO" IOSTANDARD = LVCMOS33;
NET "REF_SCLK" IOSTANDARD = LVCMOS33;
NET "REF_CONVSTART" IOSTANDARD = LVCMOS33;
NET "PORT2_SDO" IOSTANDARD = LVCMOS33;
NET "PORT2_SCLK" IOSTANDARD = LVCMOS33;
NET "PORT2_CONVSTART" IOSTANDARD = LVCMOS33;
NET "PORT1_SDO" IOSTANDARD = LVCMOS33;
NET "PORT1_SCLK" IOSTANDARD = LVCMOS33;
NET "PORT1_CONVSTART" IOSTANDARD = LVCMOS33;
NET "MCU_SCK" IOSTANDARD = LVCMOS33;
NET "MCU_NSS" IOSTANDARD = LVCMOS33;
NET "MCU_MISO" IOSTANDARD = LVCMOS33;
NET "MCU_MOSI" IOSTANDARD = LVCMOS33;
NET "MCU_INTR" IOSTANDARD = LVCMOS33;
NET "MCU_AUX2" IOSTANDARD = LVCMOS33;
NET "MCU_AUX3" IOSTANDARD = LVCMOS33;
NET "TRIGGER_IN" IOSTANDARD = LVCMOS33;
NET "TRIGGER_OUT" IOSTANDARD = LVCMOS33;

NET "ATTENUATION[6]" LOC = P9;
NET "ATTENUATION[5]" LOC = P10;
NET "ATTENUATION[4]" LOC = P11;
NET "ATTENUATION[3]" LOC = P12;
NET "ATTENUATION[2]" LOC = P14;
NET "ATTENUATION[1]" LOC = P15;
NET "ATTENUATION[0]" LOC = P16;
NET "LEDS[0]" LOC = P87;
NET "LEDS[1]" LOC = P92;
NET "LEDS[2]" LOC = P93;
NET "LEDS[3]" LOC = P88;
NET "LEDS[4]" LOC = P85;
NET "LEDS[5]" LOC = P84;
NET "LEDS[6]" LOC = P83;
NET "LEDS[7]" LOC = P82;
NET "AMP_PWDN" LOC = P8;
NET "BAND_SELECT_HIGH" LOC = P21;
NET "BAND_SELECT_LOW" LOC = P17;
NET "CLK" LOC = P50;
NET "FILT_IN_C1" LOC = P26;
NET "FILT_IN_C2" LOC = P24;
NET "FILT_OUT_C1" LOC = P22;
NET "FILT_OUT_C2" LOC = P23;
NET "LO1_CE" LOC = P45;
NET "LO1_CLK" LOC = P48;
NET "LO1_LD" LOC = P56;
NET "LO1_LE" LOC = P46;
NET "LO1_MOSI" LOC = P47;
NET "LO1_MUX" LOC = P51;
NET "LO1_RF_EN" LOC = P55;
NET "MCU_AUX1" LOC = P78;
NET "MCU_AUX2" LOC = P75;
NET "MCU_AUX3" LOC = P74;
NET "TRIGGER_IN" LOC = P80;
NET "TRIGGER_OUT" LOC = P81;
NET "MCU_INTR" LOC = P59;
NET "MCU_MISO" LOC = P62;
NET "MCU_MOSI" LOC = P61;
NET "MCU_NSS" LOC = P67;
NET "MCU_SCK" LOC = P66;
NET "MCU_SCK" CLOCK_DEDICATED_ROUTE = FALSE;

# PlanAhead Generated physical constraints 

NET "PORT1_CONVSTART" LOC = P139;
NET "PORT1_MIX1_EN" LOC = P141;
NET "PORT1_MIX2_EN" LOC = P140;
NET "PORT1_SCLK" LOC = P137;
NET "PORT1_SDO" LOC = P138;
NET "PORT1_SELECT" LOC = P142;
NET "PORT2_CONVSTART" LOC = P44;
NET "PORT2_MIX1_EN" LOC = P58;
NET "PORT2_MIX2_EN" LOC = P57;
NET "PORT2_SCLK" LOC = P41;
NET "PORT2_SDO" LOC = P43;
NET "PORT2_SELECT" LOC = P40;
NET "PORT_SELECT1" LOC = P6;
NET "PORT_SELECT2" LOC = P7;
NET "REF_CONVSTART" LOC = P5;
NET "REF_MIX1_EN" LOC = P144;
NET "REF_MIX2_EN" LOC = P143;
NET "REF_SCLK" LOC = P1;
NET "REF_SDO" LOC = P2;
NET "RESET" LOC = P79;
NET "SOURCE_CE" LOC = P27;
NET "SOURCE_CLK" LOC = P32;
NET "SOURCE_LD" LOC = P35;
NET "SOURCE_LE" LOC = P29;
NET "SOURCE_MOSI" LOC = P30;
NET "SOURCE_MUX" LOC = P33;
NET "SOURCE_RF_EN" LOC = P34;

# PlanAhead Generated IO constraints 

NET "BAND_SELECT_HIGH" IOSTANDARD = LVCMOS33;
NET "BAND_SELECT_LOW" IOSTANDARD = LVCMOS33;
NET "PORT1_MIX1_EN" IOSTANDARD = LVCMOS33;
NET "PORT1_MIX2_EN" IOSTANDARD = LVCMOS33;
NET "PORT1_SELECT" IOSTANDARD = LVCMOS33;
NET "PORT2_MIX1_EN" IOSTANDARD = LVCMOS33;
NET "PORT2_MIX2_EN" IOSTANDARD = LVCMOS33;
NET "PORT2_SELECT" IOSTANDARD = LVCMOS33;
NET "PORT_SELECT1" IOSTANDARD = LVCMOS33;
NET "PORT_SELECT2" IOSTANDARD = LVCMOS33;
NET "REF_MIX1_EN" IOSTANDARD = LVCMOS33;
NET "REF_MIX2_EN" IOSTANDARD = LVCMOS33;
