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https://github.com/yuzu-mirror/dynarmic.git
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87 lines
3.6 KiB
C++
87 lines
3.6 KiB
C++
/* This file is part of the dynarmic project.
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* Copyright (c) 2020 MerryMage
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* SPDX-License-Identifier: 0BSD
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*/
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#include "common/bit_util.h"
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#include "frontend/A32/translate/impl/translate_arm.h"
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namespace Dynarmic::A32 {
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namespace {
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template <bool WithDst, typename Callable>
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bool BitwiseInstruction(ArmTranslatorVisitor& v, bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm, Callable fn) {
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if (Q && (Common::Bit<0>(Vd) || Common::Bit<0>(Vn) || Common::Bit<0>(Vm))) {
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return v.UndefinedInstruction();
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}
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const auto d = ToVector(Q, Vd, D);
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const auto m = ToVector(Q, Vm, M);
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const auto n = ToVector(Q, Vn, N);
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if constexpr (WithDst) {
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const IR::U128 reg_d = v.ir.GetVector(d);
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const IR::U128 reg_m = v.ir.GetVector(m);
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const IR::U128 reg_n = v.ir.GetVector(n);
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const IR::U128 result = fn(reg_d, reg_n, reg_m);
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v.ir.SetVector(d, result);
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} else {
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const IR::U128 reg_m = v.ir.GetVector(m);
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const IR::U128 reg_n = v.ir.GetVector(n);
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const IR::U128 result = fn(reg_n, reg_m);
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v.ir.SetVector(d, result);
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}
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return true;
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}
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} // Anonymous namespace
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bool ArmTranslatorVisitor::asimd_VAND_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.VectorAnd(reg_n, reg_m);
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});
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}
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bool ArmTranslatorVisitor::asimd_VBIC_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.VectorAnd(reg_n, ir.VectorNot(reg_m));
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});
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}
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bool ArmTranslatorVisitor::asimd_VORR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.VectorOr(reg_n, reg_m);
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});
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}
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bool ArmTranslatorVisitor::asimd_VORN_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.VectorOr(reg_n, ir.VectorNot(reg_m));
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});
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}
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bool ArmTranslatorVisitor::asimd_VEOR_reg(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<false>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_n, const auto& reg_m) {
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return ir.VectorEor(reg_n, reg_m);
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});
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}
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bool ArmTranslatorVisitor::asimd_VBSL(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<true>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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return ir.VectorOr(ir.VectorAnd(reg_n, reg_d), ir.VectorAnd(reg_m, ir.VectorNot(reg_d)));
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});
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}
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bool ArmTranslatorVisitor::asimd_VBIT(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<true>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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return ir.VectorOr(ir.VectorAnd(reg_n, reg_m), ir.VectorAnd(reg_d, ir.VectorNot(reg_m)));
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});
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}
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bool ArmTranslatorVisitor::asimd_VBIF(bool D, size_t Vn, size_t Vd, bool N, bool Q, bool M, size_t Vm) {
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return BitwiseInstruction<true>(*this, D, Vn, Vd, N, Q, M, Vm, [this](const auto& reg_d, const auto& reg_n, const auto& reg_m) {
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return ir.VectorOr(ir.VectorAnd(reg_d, reg_m), ir.VectorAnd(reg_n, ir.VectorNot(reg_m)));
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});
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}
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} // namespace Dynarmic::A32
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