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12 commits

Author SHA1 Message Date
MerryMage 11cec1e3b6 asimd_three_same: Use {Get,Set}Vector 2020-05-28 21:05:16 +01:00
Lioncash c4a4bdd7de frontend: Relocate ExtReg handling to types.h 
Same behavior, but deduplicates the code being placed across several
files
 2020-05-24 23:55:47 +01:00
Lioncash eb332b3836 asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction 
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
 2020-05-16 20:22:12 +01:00
Lioncash f42b3ad4a0 A32: Implement ASIMD VBIF (register) 2020-05-16 20:22:12 +01:00
Lioncash ee9a81dcba A32: Implement ASIMD VBIT (register) 2020-05-16 20:22:12 +01:00
Lioncash d624059ead A32: Implement ASIMD VBSL (register) 2020-05-16 20:22:12 +01:00
Lioncash 66663cf8e7 asimd_three_same: Collapse all bitwise implementations into a single code path 
Less code and results in only writing the parts that matter once.
 2020-05-16 20:22:12 +01:00
Lioncash 4b5e3437cf A32: Implement ASIMD VEOR (register) 2020-05-16 20:22:12 +01:00
Lioncash 67b284f6fa A32: Implement ASIMD VORN (register) 2020-05-16 20:22:12 +01:00
Lioncash 1fdd90ca2a A32: Implement ASIMD VORR (register) 2020-05-16 20:22:12 +01:00
Lioncash 64fa804dd4 A32: Implement ASIMD VBIC (register) 2020-05-16 20:22:12 +01:00
Lioncash 0441ab81a1 A32: Implement ASIMD VAND (register) 2020-05-16 20:22:12 +01:00