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Author SHA1 Message Date
MerryMage f58e247ef3 A32: Implement ASIMD VPADD (floating-point) 2020-06-20 14:25:04 +01:00
MerryMage e006f0a205 A32: Implement ASIMD VSUB (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage 4c939b9d0a A32: Implement ASIMD VADD (floating-point) 2020-06-20 14:20:28 +01:00
MerryMage 5ec8e48593 A32: Implement ASIMD VMUL (floating-point) 
* Also add fpcr_controlled arguments to FPVectorMul IR instruction
* Merge ASIMD floating-point instruction implementations
 2020-06-20 14:20:28 +01:00
MerryMage bb4f3aa407 A32: Implement ASIMD VMAX, VMIN (floating-point) 2020-06-20 03:21:07 +01:00
Lioncash 8d067d5d60 A32: Implement ASIMD VMUL (integer and polynomial) 2020-06-20 00:53:56 +01:00
Lioncash ed6ca58058 A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero 
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.

In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
 2020-06-20 00:50:40 +01:00
MerryMage 656419286c ir: Add fpcr_controlled argument to FPVector{Equal,Greater,GreaterEqual} 2020-06-20 00:50:40 +01:00
MerryMage 1b3a70a83c backend/x64: Implement separate MSXCSR for ASIMDStandardValue 2020-06-20 00:00:36 +01:00
MerryMage d3664b03fe ir_emitter: Default fpcr_controlled arguments to true 2020-06-19 22:51:23 +01:00
Lioncash 794440cf8d A32: Implement ASIMD VRSHL 2020-06-19 21:27:48 +01:00
Lioncash 682621ef1a A32: Implement ASIMD VQSHL (register) 2020-06-19 21:27:48 +01:00
Lioncash e46fb98cc5 A32: Implement ASIMD VSHL (register) 2020-06-19 21:27:48 +01:00
MerryMage ad96b2b18d VFPv5: Implement VCVT{A,N,P,M} 2020-06-19 20:31:43 +01:00
MerryMage 6a965b80d6 VFPv5: Implement VRINT{A,N,P,M} 2020-06-19 20:24:13 +01:00
MerryMage 3e252cdbfc VFPv5: Implement VSEL 2020-06-19 19:44:45 +01:00
MerryMage 669d05caca VFPv5: Implement VMINNM 2020-06-19 19:44:45 +01:00
MerryMage 6e7ea151a3 VFPv5: Implement VMAXNM 2020-06-19 19:39:01 +01:00
MerryMage 4df3b2f97f vfp: Add decoders for VFPv5 
These instructions were introduced in the Cortex-M7
 2020-06-19 19:24:32 +01:00
MerryMage 55c021fe82 emit_x64_aes: AESNI implementations of all opcodes 2020-06-19 12:11:45 +01:00
Lioncash 551e207661 A32: Implement ASIMD VSUB (integer) 2020-06-19 11:31:38 +01:00
Lioncash 4d6f68525d A32: Implement ASIMD VADD (integer) 2020-06-19 11:31:38 +01:00
Lioncash fbdae61c13 A32: Implement ASIMD VMVN (register) 
Fairly straightforward
 2020-06-19 11:31:14 +01:00
MerryMage b759773b3b a32_emit_x64: EmitVAddrLookup: Use 64-bit registers where required 2020-06-19 00:44:52 +01:00
merry 687c604197
Merge pull request #532 from lioncash/shift 
A32: Implement several ASIMD shift instructions
 2020-06-19 00:22:18 +01:00
MerryMage 7dd9901de2 a32_emit_x64: Incorrect type in ExclusiveWriteMemory 2020-06-19 00:19:46 +01:00
Lioncash 00b2f9b319 asimd: Prevent misdecodes from occurring 
Pointed out by Mary when reviewing the shift code.
 2020-06-18 15:04:48 -04:00
MerryMage 87f6e412d0 emit_x64_vector: SSE4.1 implementation of EmitVectorPolynomialMultiply{Long}8 2020-06-18 18:44:00 +01:00
MerryMage f5b41aabc6 emit_x64_vector: Implement EmitVectorPolynomialMultiplyLong64 in terms of pclmulqdq 2020-06-18 18:04:23 +01:00
MerryMage 7402d38675 test_arm_instructions: Add vclt.f32 (zero) test 2020-06-18 17:59:44 +01:00
MerryMage d34763242c Revert "A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero" 
This reverts commit 179951b10f.

These instructions require StandardFPSCRValue.
 2020-06-18 17:38:40 +01:00
Lioncash 179951b10f A32: Implement ASIMD VCEQ, VCGE, VCGT, VCLE, VCLT with zero 
Fairly self-explanatory, we can leverage the existing IR functions for
the purpose of these instructions.

In the integer case, we can just insert function pointers
into an array and index it, given all comparison primitives exist
already for the integer side of things.
 2020-06-18 17:01:57 +01:00
Lioncash 6ca20c2fe3 A32: Implement ASIMD VSLI 2020-06-18 11:51:08 -04:00
Lioncash 887732d8a8 A32: Implement ASIMD VSRI 2020-06-18 11:28:12 -04:00
Lioncash 8b98c91ecc A32: Implement ASIMD VSHL 2020-06-18 11:18:33 -04:00
Lioncash 69c999bc66 A32: Implement ASIMD VRSRA 
Now that we have the accumulation and rounding code in place, VRSRA is
extremely trivial to implement.
 2020-06-18 11:03:39 -04:00
Lioncash 14fdd15199 A32: Implement ASIMD VRSHR 2020-06-18 11:00:45 -04:00
Lioncash 276e0b71dc A32: Implement ASIMD VSRA 2020-06-18 11:00:27 -04:00
Lioncash 054dff7cd5 A32: Implement ASIMD VTST 2020-06-18 15:34:05 +01:00
Lioncash 6c142bc5cc A32: Implement ASIMD VSHR 2020-06-18 10:30:20 -04:00
MerryMage 13367a7efd A64: Match A32 page_table code 
Here we increase the similarity between the A64 and A32 front-ends in terms of their
page_table handling code. In this commit, we:

* Reserve and use r14 as a register to store the page_table pointer.
* Align the code to be more similar in structure.
* Add a conf member to A32EmitContext.
* Remove scratch argument from EmitVAddrLookup.
 2020-06-18 12:22:59 +01:00
Lioncash 08350d06f1 A32: Implement ASIMD VQNEG 2020-06-18 09:49:29 +01:00
Lioncash f6b665f5a4 A32: Implement ASIMD VQABS 2020-06-18 09:49:29 +01:00
MerryMage b88c291f81 A32: Detect misaligned memory accesses 
This avoids issues with misaligned memory accesses writing into the next page.
 2020-06-17 17:51:37 +01:00
MerryMage 9f3277540a Merge A32 and A64 exclusive monitors 2020-06-17 10:33:09 +01:00
Lioncash 4b371c0445 A32: Implement ASIMD VREV{16, 32, 64} 2020-06-17 10:21:59 +01:00
Lioncash 6dd2c94095 A32: Implement ASIMD VABS 
Very similar to VNEG in that the only thing that differs is the function
called.
 2020-06-16 22:42:18 +01:00
MerryMage 53422bec46 a64_emit_x64: Reduce code duplication in exclusive memory code 2020-06-16 18:16:33 +01:00
MerryMage a1c9bb94a8 A32: Add yuzu-specific hacks 2020-06-16 17:54:21 +01:00
MerryMage 2c1a4843ad A32 global exlcusive monitor 2020-06-16 17:54:21 +01:00