yuzu-mirror/dynarmic
1
0
Fork 0
mirror of https://github.com/yuzu-mirror/dynarmic.git synced 2026-01-10 18:40:03 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity
894 commits 1 branch 0 tags 34 MiB
Commit graph

894 commits

This branch
This branch
All branches
Author SHA1 Message Date
MerryMage bf2cd92da9 emit_x64_vector: Add SSE4.1 implementation for EmitVectorMultiply64 2020-04-22 20:46:14 +01:00
MerryMage b062266b8e emit_x64_vector: More explicit lambda decay 2020-04-22 20:46:14 +01:00
MerryMage 3afd2fcbad A64: Implement MUL (vector) 2020-04-22 20:46:14 +01:00
MerryMage b6de612e01 IR: Implement VectorMultiply 2020-04-22 20:46:14 +01:00
MerryMage 90a053a5e4 emit_x64_vector: Order alphabetically 2020-04-22 20:46:14 +01:00
MerryMage e7041d7196 A64: Implement STR (register, SIMD&FP), LDR (register, SIMD&FP) 2020-04-22 20:46:14 +01:00
MerryMage a455ff70c9 decoder/a64: Don't rearrange unrelated decoders 2020-04-22 20:46:14 +01:00
MerryMage faeb77e8c4 A64: Implement SUB (vector) 2020-04-22 20:46:14 +01:00
MerryMage bd106c3ae7 A64: Implement SIMD instruction SSRA, vector variant 2020-04-22 20:46:14 +01:00
MerryMage f58aba9871 A64: Implement SIMD instruction SSHR, vector variant 2020-04-22 20:46:14 +01:00
MerryMage 715ae1c229 IR: Implement VectorArithmeticShiftRight 2020-04-22 20:46:14 +01:00
MerryMage 653c82d8f0 impl: Improve Vpart setter 2020-04-22 20:46:14 +01:00
MerryMage e858ce0b35 A64: Implement SIMD instructions XTN, XTN2 2020-04-22 20:46:13 +01:00
MerryMage 132c783320 IR: Implement VectorNarrow 2020-04-22 20:46:13 +01:00
MerryMage 1423584f9f constant_pool: Allow for 128-bit constants 2020-04-22 20:46:13 +01:00
MerryMage 69de50a878 emit_x64_vector: Add SSE4.1 implementations for VectorZeroExtend 2020-04-22 20:46:13 +01:00
MerryMage cbc9f361b0 IR: Implement VectorSub 2020-04-22 20:46:13 +01:00
MerryMage 3f93c77ace A64: Implement SIMD instruction USRA, vector variant 2020-04-22 20:46:13 +01:00
MerryMage fb9d20f27f A64: Implement SIMD instruction USHR, vector variant 2020-04-22 20:46:13 +01:00
MerryMage b22c5961f9 IR: Implement VectorLogicalShiftRight 2020-04-22 20:46:13 +01:00
MerryMage 7ff280827b A64: Implement SIMD instructions USHLL, USHLL2 2020-04-22 20:46:13 +01:00
MerryMage 59ace60b03 IR: Implement VectorZeroExtend 2020-04-22 20:46:13 +01:00
MerryMage d3a4e1efe2 IR: Vector instructions now take esize argument in emitter 2020-04-22 20:46:13 +01:00
MerryMage 1d0cd95b23 A64: Implement SIMD instruction SHL 2020-04-22 20:46:13 +01:00
MerryMage f6247125c0 IR: Implement VectorLogicalShiftLeft{8,16,32,64} 2020-04-22 20:46:13 +01:00
MerryMage 15e8231f24 opcodes: Sort vector IR opcodes alphabetically 2020-04-22 20:46:13 +01:00
MerryMage d74f4e35f6 block_of_code: Increase constant pool size 2020-04-22 20:46:13 +01:00
MerryMage e69288f803 devirtualize: MinGW uses Intanium MFP ABI 2020-04-22 20:46:13 +01:00
MerryMage ad428cbd7a callback: Properly handle calls with return pointers and simplify interface 2020-04-22 20:46:13 +01:00
FernandoS27 15871910af Implemented BSL, BIC, BIT and BIF vector instructions 2020-04-22 20:46:13 +01:00
MerryMage 7a87e3fc55 devirtualize: Handle Windows ABI 2020-04-22 20:46:13 +01:00
MerryMage 12173a8792 travis: Switch to yuzu-emu's unicorn repository 2020-04-22 20:46:13 +01:00
MerryMage a78e13ff19 fuzz_arm: Use SCOPE_FAIL 2020-04-22 20:46:13 +01:00
MerryMage ba4a779c62 A32/decoder/arm: bug: Correct bitstring for SRS 2020-04-22 20:46:13 +01:00
MerryMage f808a0fbde devirtualize: Devirtualize Itanium ABI MFPs at runtime 2020-04-22 20:46:13 +01:00
MerryMage afe16fa0f3 cast_util: Add BitCast and BitCastPointee 2020-04-22 20:46:13 +01:00
Lioncash 4e33629b0e A64: Move SDIV and UDIV out of data_processing_multiply.cpp 2020-04-22 20:46:13 +01:00
Lioncash 35a29a9665 A64: Implement ZIP1 2020-04-22 20:46:13 +01:00
FernandoS27 586854117b Implemented UMULH and SMULH instructions 2020-04-22 20:46:13 +01:00
MerryMage 1a7b7b541a A64: Implement MOVI, MVNI, ORR (vector, immediate), BIC (vector, immediate) 
There wasn't a clean way to seperate these instructions out.
 2020-04-22 20:46:13 +01:00
MerryMage 8ab7d8175c impl: Add AdvSIMDExpandImm 2020-04-22 20:46:13 +01:00
MerryMage ea69cb4474 A64: Implement SUB (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage 4c5871d5d5 A64: Implement ADD (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage 2a0850c068 A64: Reorganize decoder tables (some vector entries were grouped with scalar entries) 2020-04-22 20:46:13 +01:00
MerryMage 7b33772ac6 A64: Implement BIC (vector, register) 2020-04-22 20:46:13 +01:00
MerryMage ca43be4146 docs: Update documentation (2018-02-05) 2020-04-22 20:46:13 +01:00
MerryMage eb5591859c A64: Implement FMOV (general) 2020-04-22 20:46:13 +01:00
MerryMage dd88cee15a translate/impl: Add Vpart 2020-04-22 20:46:13 +01:00
MerryMage cc9efd13c9 A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR 2020-04-22 20:46:13 +01:00
MerryMage 81713c2b77 A64: Implement FCCMPE 2020-04-22 20:46:13 +01:00