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Author SHA1 Message Date
Merry 9bdff6a9aa constant_propagation_pass: Shift with non-zero value does not require c flag as input 2022-10-18 15:04:30 +01:00
Merry 5a864f41c6 backend/arm64/reg_alloc: Implement DefineAsRegister 2022-10-18 15:04:30 +01:00
Merry 16701ae6d5 backend/arm64/reg_alloc: Use NZCV instead of magic numbers 2022-10-18 15:04:30 +01:00
Merry ba00b3586c oaknut: Add common system registers 2022-10-18 15:04:30 +01:00
Merry c2ff75e29c backend/arm64: Implement Sub 2022-10-18 15:04:30 +01:00
Merry 8ac57bd6ed backend/arm64/reg_alloc: Assert on bad RAReg 2022-10-18 15:04:30 +01:00
Merry 78bc0812b9 backend/arm64/reg_alloc: More flag handling 2022-10-18 15:04:30 +01:00
Merry 21601764de backend/arm64: Implement Add 2022-10-18 15:04:30 +01:00
Merry 679efb9c44 backend/arm64: Implement A32SetCpsrNZCV 2022-10-18 15:04:30 +01:00
Merry 67df13f886 backend/arm64: Update for new C flag representation 2022-10-18 15:04:30 +01:00
Merry d69582f548 backend/arm64/reg_alloc: Tidy up HostLocInfo 2022-10-18 15:04:30 +01:00
Merry 01f28facbd abi: Add Rscratch{0,1} 2022-10-18 15:04:30 +01:00
Merry 8b41755db0 ir_emitter: Remove unused ResultAndCarryAndOverflow structure 2022-10-18 15:04:30 +01:00
Merry b6bb94872a backend/arm64: Implement IsZero64 2022-10-18 15:04:30 +01:00
Merry 3821c4a16b backend/arm64: Implement MostSignificantWord 2022-10-18 15:04:30 +01:00
Merry ec3c597591 backend/arm64: Implement LeastSignificantByte 2022-10-18 15:04:30 +01:00
Merry a33d186fea backend/arm64: Implement LeastSignificantHalf 2022-10-18 15:04:30 +01:00
Merry 163ed9b185 backend/arm64: Implement LeastSignificantWord 2022-10-18 15:04:30 +01:00
Merry 7c86b06233 backend/arm64: Implement Pack2x64To1x128 2022-10-18 15:04:30 +01:00
Merry 98806139a5 backend/arm64/reg_alloc: Argument HostLoc location 2022-10-18 15:04:30 +01:00
Merry fe4e864e4c backend/arm64: Implement Pack2x32To1x64 2022-10-18 15:04:30 +01:00
Merry ff9b92c791 backend/arm64: Implement NZCVFromPackedFlags 2022-10-18 15:04:30 +01:00
Merry 7ea97f7629 backend/arm64: Implement GetLowerFromOp 2022-10-18 15:04:30 +01:00
Merry 92026a456a backend/arm64: Implement GetUpperFromOp 2022-10-18 15:04:30 +01:00
Merry 8c4ea10a38 backend/arm64: Implement GetNZCVFromOp 2022-10-18 15:04:30 +01:00
Merry e34749336a backend/arm64: Implement GetGEFromOp 2022-10-18 15:04:30 +01:00
Merry fbcbc1d90d backend/arm64: Implement GetOverflowFromOp 2022-10-18 15:04:30 +01:00
Merry fb3b828158 backend/arm64: Implement Identity 2022-10-18 15:04:30 +01:00
Merry 97ba8a0f14 backend/arm64: Implement Void 2022-10-18 15:04:30 +01:00
Merry 2a24bb2c1e backend/arm64: Implement Breakpoint 2022-10-18 15:04:30 +01:00
Merry 3a11467220 backend/arm64: Stub all IR instruction implementations 2022-10-18 15:04:30 +01:00
Merry 402abf5ea3 backend/arm64: Implement A32GetExtendedRegister 2022-10-18 15:04:30 +01:00
Merry 84cad9f831 backend/arm64: Implement A32SetCheckBit 2022-10-18 15:04:30 +01:00
Merry 3e5309bd96 tests: Add test generator 2022-10-18 15:04:30 +01:00
Merry 52a46d841b backend/arm64: Implement A32BXWritePC 2022-10-18 15:04:30 +01:00
Merry 67dc7f2e4e backend/arm64: Implement A32UpdateUpperLocationDescriptor 2022-10-18 15:04:30 +01:00
Merry 00ad84b7ab backend/arm64: Initial implementation of terminals 2022-10-18 15:04:30 +01:00
Merry 80c89401b9 a32_address_space: Add StackLayout to stack 2022-10-18 15:04:30 +01:00
Merry 9b2391ec7b backend/arm64/reg_alloc: Implement AssertNoMoreUses 2022-10-18 15:04:30 +01:00
Merry ecacb6cdc6 tests/rand_int: Expose PRNG 2022-10-18 15:04:30 +01:00
Merry 8e6467bf45 backend/arm64/reg_alloc: Add flag handling 2022-10-18 15:04:30 +01:00
Merry 77436bbbbb backend/arm64: Toy implementation of enough to execute LSLS 2022-10-18 15:04:30 +01:00
Merry 7e046357ff backend/arm64: Initial implementation of register allocator 2022-10-18 15:04:30 +01:00
Merry 3bf2b0aba9 backend/arm64: Adjust how relocations are stored 2022-10-18 15:04:30 +01:00
Merry e0f091b6a6 backend/arm64: void* -> CodePtr 2022-10-18 15:04:30 +01:00
Merry f6e80f1e0e backend/arm64: First dummy code execution 2022-10-18 15:04:30 +01:00
Merry d877777c50 backend/arm64: Initial framework 2022-10-18 15:04:30 +01:00
Merry e7b2eb2c7c Add aarch64 CI 2022-10-18 15:04:30 +01:00
Wunkolo e886bfb7c1 backend/x64: Fix FixupLUT argument order 
The last two arguments(fixup response response for finite values) are
neg-pos, not pos-neg. Found this out while re-using this function for
some math stuff. Thankfully nothing currently uses this fixup response
at the moment.
 2022-09-30 23:10:21 +01:00
Merry af51845a53 decoder_detail: Workaround #708 2022-09-02 21:16:43 +01:00