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808 commits 1 branch 0 tags 34 MiB
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12 commits

Author SHA1 Message Date
MerryMage 99d8ebe4d5 A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar) 2020-04-22 20:46:13 +01:00
MerryMage d7044bc751 assert: Use fmt in ASSERT_MSG 2020-04-22 20:46:12 +01:00
MerryMage b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
MerryMage 0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage aa74a8130b Misc. fixups of MSVC build 2020-04-22 20:42:45 +01:00
MerryMage 25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage 0641445e51 A64: Implement logical 2020-04-22 20:42:45 +01:00
MerryMage c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00