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Author SHA1 Message Date
James Rowe 3aeb7ca50c Add missing returns 2020-04-22 20:44:38 +01:00
James Rowe 41e6e659c5 A64: Implement Load/Store register (unprivileged) 2020-04-22 20:44:37 +01:00
MerryMage 01a26fa644 fixup: travis: Test with disabled CPU feature detection 2020-04-22 20:44:37 +01:00
Lioncash 5281d3c6d5 CMakeLists: Add opcodes.inc to the source file list 
Allows the file to show up nicely within IDEs
 2020-04-22 20:44:37 +01:00
MerryMage 30936f5e94 travis: Test with disabled CPU feature detection 
Ensure that fallbacks are working correctly.
 2020-04-22 20:44:37 +01:00
MerryMage 285fd22c30 IR: Add IR instruction VectorZeroUpper 2020-04-22 20:44:37 +01:00
MerryMage da3e9a5704 a64_emit_x64: bug: EmitA64WriteMemory128 should write not read 2020-04-22 20:44:37 +01:00
FernandoS27 ab84524806 Implemented SDIV and UDIV instructions 2020-04-22 20:44:37 +01:00
MerryMage 6033b05ca6 A64: Implement LDR/STR (immediate, SIMD&FP) 2020-04-22 20:44:37 +01:00
MerryMage f698848e26 IR: Add IR instructions A64Memory{Read,Write}128 
Add the Windows ABI implementation
 2020-04-22 20:44:37 +01:00
MerryMage e1df7ae621 IR: Add IR instructions A64Memory{Read,Write}128 
This implementation only works on macOS and Linux.
 2020-04-22 20:44:37 +01:00
MerryMage e00a522cba IR: Add IR instruction VectorGetElement{8,16,32,64} 2020-04-22 20:44:37 +01:00
MerryMage 28ccd85e5c IR: Add IR instruction ZeroExtendToQuad 2020-04-22 20:44:37 +01:00
MerryMage af848c627d block_of_code: Add ABI_RETURN2 2020-04-22 20:44:37 +01:00
MerryMage 1749780929 interface: Move Vector typedef to config.h 2020-04-22 20:44:37 +01:00
MerryMage 33bba6028c bit_util: bug: Infinite loop in HighestSetBit 2020-04-22 20:44:37 +01:00
MerryMage 3caf192f60 A64: Implement DUP (general) 2020-04-22 20:44:37 +01:00
MerryMage 793753bf63 IR: Implement Vector{Lower,}Broadcast{8,16,32,64} 2020-04-22 20:44:37 +01:00
Lioncash 8ee854232c General: Default constructors and destructors where applicable 2020-04-22 20:44:37 +01:00
Lioncash d1e4526e1c ir_emitter: Remove unused includes 2020-04-22 20:44:37 +01:00
Lioncash 6f9216d544 A64: Implement RBIT 2020-04-22 20:44:37 +01:00
MerryMage 9b0a21915f ir_emitted: Remove unimplemented IR instruction Unimplemented 2020-04-22 20:44:37 +01:00
MerryMage db30e02ac8 emit_x64: Extract BlockRangeInformation, remove template parameter 2020-04-22 20:44:36 +01:00
MerryMage 58c4a25527 emit_x64: Use JitStateInfo 2020-04-22 20:42:46 +01:00
MerryMage d4b05b28cf A64: Implement CLS 
This is not the cleanest implementation.
 2020-04-22 20:42:46 +01:00
MerryMage b8e26bfdc3 A64: Implement ADDP (vector) 2020-04-22 20:42:46 +01:00
MerryMage eaf545877a IR: Implement Vector{Lower,}PairedAdd{8,16,32,64} 2020-04-22 20:42:46 +01:00
MerryMage a554e4a329 backend_x64: Split emit_x64 2020-04-22 20:42:46 +01:00
MerryMage 2a493f8b50 fuzz_with_unicorn: Compare vectors 2020-04-22 20:42:46 +01:00
MerryMage 394bd57bb6 microinstruction: bug: Add missing opcodes 2020-04-22 20:42:46 +01:00
Lioncash bb1c5bd3b2 A64: Implement SMADDL, SMSUBL, UMADDL, and UMSUBL 2020-04-22 20:42:46 +01:00
Lioncash c1a25bfc2f A64: Implement MADD and MSUB 2020-04-22 20:42:46 +01:00
Lioncash b7c5055d42 A64: Implement CLZ 2020-04-22 20:42:46 +01:00
Lioncash b612782445 opcodes: Add 64-bit CountLeadingZeroes opcode 2020-04-22 20:42:46 +01:00
MerryMage 4c4efb2213 data_processing_register: Clean-up 2020-04-22 20:42:46 +01:00
Lioncash ae5dbcbed6 A64: Implement HINT, NOP, YIELD, WFE, WFI, SEV, and SEVL 
Truly the most difficult A64 instructions to implement.
 2020-04-22 20:42:46 +01:00
Lioncash 4d8f4aa8af A64: Implement ASRV, LSLV, LSRV, and RORV 2020-04-22 20:42:46 +01:00
Lioncash a8a65beb2b data_processsing_conditional_select: Implement CSINC, CSINV and CSNEG 2020-04-22 20:42:46 +01:00
Lioncash b08be71775 a32/a64_emit_x64: Remove unused includes 2020-04-22 20:42:46 +01:00
MerryMage f81d0a2536 A64: Implement AND (vector) 2020-04-22 20:42:46 +01:00
MerryMage 35aaee6cc6 tests/A64: Randomize vectors 2020-04-22 20:42:46 +01:00
MerryMage 33a02ed91a tests/A64/unicorn: Print interrupt number when InterruptHook is hit 2020-04-22 20:42:46 +01:00
MerryMage e9f6e7c82c tests/A64: Allow RunTestInstance to start from an arbitrary offset 2020-04-22 20:42:46 +01:00
MerryMage a63fc6c89b A64: Implement ADD (vector, vector) 2020-04-22 20:42:46 +01:00
Thomas Guillemard 896cf44f96 A64: Implement REV, REV32, and REV16 (#126) 2020-04-22 20:42:46 +01:00
MerryMage 5eb0bdecdf IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 
ARM's Architecture Specification Language doesn't distinguish between floats and integers
as much as we do. This makes some things difficult to implement. Since our register
allocator is now capable of allocating values to XMMs and GPRs as necessary, the
Transfer IR instructions are no longer necessary as they used to be and they can be
removed.
 2020-04-22 20:42:46 +01:00
MerryMage 9a812b0c61 reg_alloc: GetBitWidth: Add UNREACHABLE 2020-04-22 20:42:46 +01:00
MerryMage fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage 144b629d8a A64: Implement CSEL 2020-04-22 20:42:45 +01:00
MerryMage 6395f09f94 IR: Implement Conditional Select 2020-04-22 20:42:45 +01:00