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Author SHA1 Message Date
MerryMage 8ab7d8175c impl: Add AdvSIMDExpandImm 2020-04-22 20:46:13 +01:00
MerryMage ea69cb4474 A64: Implement SUB (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage 4c5871d5d5 A64: Implement ADD (vector), scalar variant 2020-04-22 20:46:13 +01:00
MerryMage 2a0850c068 A64: Reorganize decoder tables (some vector entries were grouped with scalar entries) 2020-04-22 20:46:13 +01:00
MerryMage 7b33772ac6 A64: Implement BIC (vector, register) 2020-04-22 20:46:13 +01:00
MerryMage ca43be4146 docs: Update documentation (2018-02-05) 2020-04-22 20:46:13 +01:00
MerryMage eb5591859c A64: Implement FMOV (general) 2020-04-22 20:46:13 +01:00
MerryMage dd88cee15a translate/impl: Add Vpart 2020-04-22 20:46:13 +01:00
MerryMage cc9efd13c9 A64: Implement STLLRB, STLLRH, STLLR, LDLARB, LDLARH, LDLAR 2020-04-22 20:46:13 +01:00
MerryMage 81713c2b77 A64: Implement FCCMPE 2020-04-22 20:46:13 +01:00
MerryMage ef906dbbfa A64: Implement FCCMP 2020-04-22 20:46:13 +01:00
MerryMage 44c3c2312a a64_jitstate: Remove unnecessary FPSCR_nzcv member 2020-04-22 20:46:13 +01:00
MerryMage aac5af50e2 IR: FPCompare{32,64} now return NZCV flags instead of implicitly setting them 2020-04-22 20:46:13 +01:00
Lioncash 2ee39d6b36 A64: Implement FMOV (register) 2020-04-22 20:46:13 +01:00
MerryMage b02b861242 A64: Implement STLRB, STLRH, STLR, LDARB, LDARH, LDAR 2020-04-22 20:46:13 +01:00
Lioncash 5a65313236 A64: Implement CCMP (immediate) 2020-04-22 20:46:13 +01:00
Lioncash ab4664de61 A64: Implement CCMN (immediate) 2020-04-22 20:46:13 +01:00
Lioncash a6c6539109 A64: Implement CCMP (register) 2020-04-22 20:46:13 +01:00
Lioncash 22632db337 microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement 2020-04-22 20:46:13 +01:00
MerryMage c5033b5dda A64: Implement CCMN (register) 2020-04-22 20:46:13 +01:00
MerryMage dd2a6684fe IR: Add ConditionalSelectNZCV instruction 2020-04-22 20:46:13 +01:00
Lioncash 12c6f841c2 inst_gen: Make invalid_instructions a static inline variable 2020-04-22 20:46:13 +01:00
Lioncash f96e83c486 fuzz_with_unicorn: Move instruction generator vector into GenRandomInst 
Keeps scope localized and prevents potential static initialization issues.
 2020-04-22 20:46:13 +01:00
MerryMage 4491746eae A64: Implement FNEG 2020-04-22 20:46:13 +01:00
MerryMage db958061a3 A64: Implement FABS 2020-04-22 20:46:13 +01:00
MerryMage 8765b421b7 A64: Implement FCSEL 2020-04-22 20:46:13 +01:00
MerryMage 7e82d8eede A64: Implement SCVTF (scalar, integer), UCVTF (scalar, integer) 2020-04-22 20:46:13 +01:00
MerryMage 2409e5d082 A64: Implement FCVTZS (scalar, integer), FCVTZU (scalar, integer) 2020-04-22 20:46:13 +01:00
MerryMage b173fcf34e backend_x64: Simplify FPDoubleToU32 and FPSingleToU32 
They're inaccurate in terms of FPSR at the moment anyway.
 2020-04-22 20:46:13 +01:00
MerryMage 56bc7825ef A64: Implement STR{,B,H} (register), LDR{,B,H,SB,SH,SW} (register), PFRM (register) 2020-04-22 20:46:13 +01:00
Lioncash d040920727 Common: Put AES code within its own nested namespace 
Prevents the functions from potentially clashing with other stuff in Common in the future
 2020-04-22 20:46:13 +01:00
Lioncash 40614202e7 A64: Implement AESD 2020-04-22 20:46:13 +01:00
Lioncash ccef85dbb7 A64: Implement AESE 2020-04-22 20:46:13 +01:00
MerryMage 68f46c8334 backend_x64: Use a reference to BlockOfCode instead of a pointer 2020-04-22 20:46:13 +01:00
MerryMage 8931ee346b IR: Add IR instruction NZCVFromPackedFlags 
This instruction expects NZCV to be in the high bits.
i.e.: The positions they were in PSTATE.
 2020-04-22 20:46:13 +01:00
MerryMage 0bb4474fb9 A64: Implement INS (general) 2020-04-22 20:46:13 +01:00
MerryMage d13704fdef A64: Implement INS (element) 2020-04-22 20:46:13 +01:00
MerryMage 0642d49919 A64: Implement SMOV 2020-04-22 20:46:13 +01:00
MerryMage 5297027ebe A64: Implement UMOV 2020-04-22 20:46:13 +01:00
MerryMage 47661b746b basic_block: Fix bogus GCC maybe-uninitialized warning 2020-04-22 20:46:13 +01:00
MerryMage 1fb0957aa3 A64: Implement FCVT 2020-04-22 20:46:13 +01:00
MerryMage ca38225e08 fuzz_with_unicorn: Skip instructions that need to be interpreted 2020-04-22 20:46:13 +01:00
MerryMage 4be55b8b84 A64: Implement FMOV (scalar, immediate) 2020-04-22 20:46:13 +01:00
MerryMage a07c05ea51 A64: Implement STUR (SIMD&FP), LDUR (SIMD&FP) 2020-04-22 20:46:13 +01:00
MerryMage 93fcbdf1e2 A64: Implement FCMP, FCMPE 2020-04-22 20:46:13 +01:00
MerryMage 75b8a76630 a64_jitstate: A64 does not have a seperate FPSCR.NZCV 2020-04-22 20:46:13 +01:00
MerryMage 99d8ebe4d5 A64: Implement FMUL (scalar), FDIV (scalar), FADD (scalar), FSUB (scalar), FNMUL (scalar) 2020-04-22 20:46:13 +01:00
MerryMage 429dc24587 IR: Merge U32 and U64 variants of FP instructions 2020-04-22 20:46:13 +01:00
MerryMage ed2bedec43 A64: Implement {ST,LD}{1,2,3,4} (multiple structures) 2020-04-22 20:46:13 +01:00
MerryMage 6414736a8d emit_x64_vector: bug: VectorGetElement8 returning incorrect values for non-SSE4.1 
This bug wasn't discovered earlier because we previously only used index == 0.
 2020-04-22 20:46:13 +01:00