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Author SHA1 Message Date
bunnei 8e8db6e137 TranslateArm: Implement VSTR. 2016-08-10 15:01:23 +01:00
MerryMage df39308e03 TranslateArm: Implement CLREX, LDREX, LDREXB, LDREXD, LDREXH, STREX, STREXB, STREXD, STREXH, SWP, SWPB 2016-08-09 22:57:20 +01:00
MerryMage d921390928 TranslateArm: Add santity check to see if we've emitted a terminal instruction 2016-08-09 22:47:41 +01:00
MerryMage 2eec43178a IR: Opaque can be of any type 2016-08-09 22:46:44 +01:00
MerryMage 29d30bf931 Interface: Added Jit::Reset to reset CPU state 2016-08-09 22:45:54 +01:00
MerryMage 82f42d065f DisassemblerArm: Implemented disassembly of STR*/LDR* instructions 2016-08-09 22:44:42 +01:00
MerryMage d0d51ba346 TranslateArm: Implement STM, STMDA, STMDB, STMIB 2016-08-08 22:49:11 +01:00
Tillmann Karras 5d26899ac9 Add simplified LogicalShiftRight64 IR opcode 2016-08-08 22:27:05 +01:00
Tillmann Karras ccb2aa96a5 Add support for the APSR.Q flag 2016-08-08 22:27:04 +01:00
Tillmann Karras 11e0688e5f Fix build on case-sensitive file systems 2016-08-08 22:27:03 +01:00
MerryMage 85549d7ae2 TranslateArm: Implement LDM, LDMDA, LDMDB, LDMIB 2016-08-08 22:26:06 +01:00
MerryMage 46e4864707 ArmTypes: Add RegListToString and reorganise 2016-08-08 22:20:28 +01:00
MerryMage 975f011fc0 BackendX64/RegAlloc: Do not allocate RSP for guest use 2016-08-08 16:01:07 +01:00
MerryMage abd113f160 EmitX64: Renamed patch_jmp_locations to patch_jg_locations 2016-08-08 15:56:07 +01:00
MerryMage 52fa998e6b EmitX64: EmitTerminalLinkBlock: Fix behaviour when setting T and E flags 2016-08-07 22:47:43 +01:00
MerryMage 04c1a0d2de EmitX64: Switch MXCSR when switching to interpreter 2016-08-07 22:47:17 +01:00
MerryMage edb236ab07 Correct implementation of thumb16_SVC and arm_SVC 2016-08-07 22:19:39 +01:00
MerryMage a32063fa60 EmitX64: Implement block linking 2016-08-07 22:11:39 +01:00
MerryMage b3bb1d5048 Tests: Tidy up ARM fuzz tests 2016-08-07 21:55:38 +01:00
MerryMage 328422b740 RegAlloc: HostCall flushes all XMM regsiters 2016-08-07 21:02:16 +01:00
MerryMage 4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC 2016-08-07 20:50:33 +01:00
MerryMage 1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ 2016-08-07 20:40:31 +01:00
MerryMage 939bb5c0cb TranslateArm: Implement NOP 2016-08-07 20:08:31 +01:00
MerryMage e48df9d8fd TranslateArm: Implement Hint instructions as NOPs 2016-08-07 20:04:48 +01:00
MerryMage 3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00
MerryMage a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage aba705f6b9 BackendX64: Merge Routines into BlockOfCode 2016-08-07 18:08:48 +01:00
MerryMage 0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage cd8e7c0504 VFP: Implement VNEG 2016-08-07 12:04:21 +01:00
MerryMage da33af5abe VFP: Implement VMLA, VMLS, VNMLA, VNMLS 2016-08-07 11:49:06 +01:00
MerryMage 3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage 12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage 97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage f88b1b4c2e FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask 2016-08-07 01:10:19 +01:00
MerryMage c35f06470f VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1 2016-08-06 23:01:18 +01:00
MerryMage 94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. 2016-08-06 22:23:01 +01:00
Tillmann Karras 9264e2e04c Use XOR when loading a zero immediate 2016-08-06 21:17:11 +01:00
Tillmann Karras 55204a80d0 Implement SMMLA, SMMLS, SMMUL 2016-08-06 21:17:11 +01:00
Tillmann Karras 846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
Tillmann Karras 01aebcb385 Remove *MulHi wrappers 2016-08-06 21:17:11 +01:00
Tillmann Karras 5e047107a0 Disassemble more instructions 
CLZ, SEL, USAD8, USADA8, SSAT, SSAT16, USAT, USAT16, SMLAL*, SMLA*,
SMUL*, SMLAW*, SMULW*, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD
 2016-08-06 21:17:11 +01:00
Tillmann Karras f99cb613cf Disassemble packs and more multiplies 2016-08-06 21:17:11 +01:00
Tillmann Karras 81d9d4b012 Add Subv's sign/zero extension tests 2016-08-06 21:17:11 +01:00
Tillmann Karras a281fcc744 Fix printf 2016-08-06 21:17:11 +01:00
MerryMage 7915f97d98 TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning) 2016-08-06 20:42:06 +01:00
MerryMage 4d127c19dd Common: Add a memory pool implementation, remove use of boost::pool 2016-08-06 20:41:00 +01:00
MerryMage 411e804b0d Interface: Forward declare Arm::LocationDescriptor 2016-08-06 20:11:35 +01:00
MerryMage 9ab7626374 Tests/VFP: Add tests for VADD.F32 2016-08-06 20:03:15 +01:00