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2258 commits 1 branch 0 tags 34 MiB
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24 commits

Author SHA1 Message Date
Lioncash 8d067d5d60 A32: Implement ASIMD VMUL (integer and polynomial) 2020-06-20 00:53:56 +01:00
Lioncash 794440cf8d A32: Implement ASIMD VRSHL 2020-06-19 21:27:48 +01:00
Lioncash 682621ef1a A32: Implement ASIMD VQSHL (register) 2020-06-19 21:27:48 +01:00
Lioncash e46fb98cc5 A32: Implement ASIMD VSHL (register) 2020-06-19 21:27:48 +01:00
Lioncash 551e207661 A32: Implement ASIMD VSUB (integer) 2020-06-19 11:31:38 +01:00
Lioncash 4d6f68525d A32: Implement ASIMD VADD (integer) 2020-06-19 11:31:38 +01:00
Lioncash 054dff7cd5 A32: Implement ASIMD VTST 2020-06-18 15:34:05 +01:00
MerryMage f3845cea9a A32: Implement ASIMD VQSUB instruction 2020-05-30 18:19:17 +01:00
MerryMage 16ff880f8f A32: Implement ASIMD VQADD 2020-05-30 16:09:37 +01:00
MerryMage 3a50d444dc A32: Implement ASIMD VHSUB 2020-05-28 22:29:00 +01:00
MerryMage 205e6c5a56 A32: Implement ASIMD VRHADD 2020-05-28 22:29:00 +01:00
MerryMage 946eb03a3b A32: Implement ASIMD VHADD 2020-05-28 22:29:00 +01:00
MerryMage 11cec1e3b6 asimd_three_same: Use {Get,Set}Vector 2020-05-28 21:05:16 +01:00
Lioncash c4a4bdd7de frontend: Relocate ExtReg handling to types.h 
Same behavior, but deduplicates the code being placed across several
files
 2020-05-24 23:55:47 +01:00
Lioncash eb332b3836 asimd_three_same: Unify BitwiseInstructionWithDst with BitwiseInstruction 
Now that all bitwise instructions are implemented, we can unify all of
them together using if constexpr.
 2020-05-16 20:22:12 +01:00
Lioncash f42b3ad4a0 A32: Implement ASIMD VBIF (register) 2020-05-16 20:22:12 +01:00
Lioncash ee9a81dcba A32: Implement ASIMD VBIT (register) 2020-05-16 20:22:12 +01:00
Lioncash d624059ead A32: Implement ASIMD VBSL (register) 2020-05-16 20:22:12 +01:00
Lioncash 66663cf8e7 asimd_three_same: Collapse all bitwise implementations into a single code path 
Less code and results in only writing the parts that matter once.
 2020-05-16 20:22:12 +01:00
Lioncash 4b5e3437cf A32: Implement ASIMD VEOR (register) 2020-05-16 20:22:12 +01:00
Lioncash 67b284f6fa A32: Implement ASIMD VORN (register) 2020-05-16 20:22:12 +01:00
Lioncash 1fdd90ca2a A32: Implement ASIMD VORR (register) 2020-05-16 20:22:12 +01:00
Lioncash 64fa804dd4 A32: Implement ASIMD VBIC (register) 2020-05-16 20:22:12 +01:00
Lioncash 0441ab81a1 A32: Implement ASIMD VAND (register) 2020-05-16 20:22:12 +01:00