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Author SHA1 Message Date
Lioncash 73b9e4b276 A64: system: Use an enum class for MRS/MSR register encodings 
Reduces the need to manually write out the register bit encodings repeatedly.
 2020-04-22 20:46:15 +01:00
MerryMage df4ee0f51e emit_X64_floating_point: Near jmp to end instead of short jmp 
Jump destination can be further than what can be reached in a short
jump under some FPCR options.
 2020-04-22 20:46:15 +01:00
Lioncash b8d5765f9b emit_x64_vector: Fix typo in VectorShuffleImpl 
This is supposed to be pshufd, not pshufw (which only allows a 64-bit operand)
 2020-04-22 20:46:15 +01:00
Lioncash 586b00d11d A64: Implement REV64 2020-04-22 20:46:15 +01:00
Lioncash ade595e377 bit_util: Do nothing in RotateRight if the rotation amount is zero 
Without this sanitizing it's possible to perform a shift with a shift
amount that's the same size as the type being shifted. This actually
occurs when decoding ORR variants.

We could get fancier here and make this branchless, but we don't
really use RotateRight in any performance intensive areas.
 2020-04-22 20:46:15 +01:00
Lioncash 9128988dc3 A64: Implement REV32 (vector) 2020-04-22 20:46:15 +01:00
Lioncash 6b0010c940 ir: Add IR opcodes for emitting vector shuffles 
This uses the ARM terminology for sizes (Halfword -> 2 bytes, Word -> 4 bytes)
as opposed to the x86 terminology of (Word -> 2 bytes, Double word -> 4 bytes)
 2020-04-22 20:46:15 +01:00
Lioncash eb2d28d2b1 emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64 2020-04-22 20:46:15 +01:00
Lioncash 6ad1bce5e0 A64: Implement REV16 (vector) 2020-04-22 20:46:15 +01:00
Lioncash 6177c2c63d CMakeLists: Add fp_util, macro_util and math_util headers 
Allows the headers to show up within IDEs
 2020-04-22 20:46:15 +01:00
Lioncash 7a66224d9a A64: Implement EOR3 and BCAX 2020-04-22 20:46:15 +01:00
Lioncash bc4bde1fbd travis: Use yuzu's unicorn fork 2020-04-22 20:46:15 +01:00
Lioncash 8e28bea0ac externals: Update catch to v2.2.1 
Keeps the testing library up to date
 2020-04-22 20:46:15 +01:00
MerryMage be5047c7c2 impl: Update PC when raising exception 2020-04-22 20:46:15 +01:00
MerryMage 49cc6d7fad A64: Implement FDIV (vector) 2020-04-22 20:46:15 +01:00
MerryMage fd075d8d68 system: Raise exception for YIELD, WFE, WFI, SEV, SEVL 2020-04-22 20:46:15 +01:00
MerryMage c832cec96d Correct FPSR and FPCR 2020-04-22 20:46:15 +01:00
MerryMage 147284427b A64: Implement USHL 2020-04-22 20:46:15 +01:00
MerryMage fd8f4c1195 A64: Implement UCVTF (vector, integer), scalar variant 2020-04-22 20:46:15 +01:00
MerryMage be57608353 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 2020-04-22 20:46:15 +01:00
MerryMage e4697b1676 A64: Implement system register TPIDR_EL0 2020-04-22 20:46:15 +01:00
MerryMage e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage 9e4e4e9c1d A64: Implement system register CNTPCT_EL0 2020-04-22 20:46:15 +01:00
MerryMage 1e15283d00 A64: Implement system register CTR_EL0 2020-04-22 20:46:15 +01:00
MerryMage 58fbb3ff1b A64: Implement NEG (vector) 2020-04-22 20:46:15 +01:00
MerryMage 710d09471b IR: Add IR instruction ZeroVector 2020-04-22 20:46:15 +01:00
MerryMage 2721bb5ace emit_x64_floating_point: Add maybe_unused to preprocess parameter 2020-04-22 20:46:15 +01:00
MerryMage 0575e7421b A64: Implement FMINNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage 1c9804ea07 A64: Implement FMAXNM (scalar) 2020-04-22 20:46:15 +01:00
MerryMage 1dfce0894d constant_pool: Add frame parameter 2020-04-22 20:46:14 +01:00
MerryMage bd2b415850 A64: Implement ADDP (scalar) 2020-04-22 20:46:14 +01:00
MerryMage 84f1c9b7f4 reg_alloc: Only exchange GPRs 2020-04-22 20:46:14 +01:00
MerryMage 9df3793af0 A64: Implement DUP (element), scalar variant 2020-04-22 20:46:14 +01:00
MerryMage 6541ec064d emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 2020-04-22 20:46:14 +01:00
MerryMage 2080a51f41 A64: Implement FMAX (scalar), FMIN (scalar) 2020-04-22 20:46:14 +01:00
MerryMage 44a5b57f2a fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 2020-04-22 20:46:14 +01:00
MerryMage eaa1fd36a7 travis: Switch unicorn repository 2020-04-22 20:46:14 +01:00
MerryMage 7c193485e1 a64/config: Allow NaN emulation accuracy to be set 2020-04-22 20:46:14 +01:00
MerryMage a3df46a75a a64_emit_x64: Add conf to A64EmitContext 2020-04-22 20:46:14 +01:00
MerryMage 1311f67b4a fuzz_with_unicorn: Explicitly test floating point instructions 2020-04-22 20:46:14 +01:00
MerryMage 0e157b0198 A64: Implement FSQRT (scalar) 2020-04-22 20:46:14 +01:00
MerryMage 07520f32c3 backend_x64: Accurately handle NaNs 2020-04-22 20:46:14 +01:00
MerryMage e97581d063 fuzz_with_unicorn: Print AArch64 disassembly 2020-04-22 20:46:14 +01:00
MerryMage 01c1e9017e T32: Add initial decoder list 2020-04-22 20:46:14 +01:00
MerryMage ccf7df057b simd_three_same: Add VectorZeroUpper to CMGE (vector) and CMHS (vector) 2020-04-22 20:46:14 +01:00
MerryMage 8cebb87d0d A64: Implement CMGT (zero), CMEQ (zero), CMLT (zero) 2020-04-22 20:46:14 +01:00
MerryMage 7f68d556ab decoder/a64: Rearrange SIMD two-register misc decoders 2020-04-22 20:46:14 +01:00
MerryMage d5af052f06 A64: Implement CMGE (register) 2020-04-22 20:46:14 +01:00
MerryMage 9d85991906 A64: Implement CMHI, CMHS 2020-04-22 20:46:14 +01:00
MerryMage e2b9b7c5b0 IR: Implement Vector{Less,Greater}{,Equal}{Signed,Unsigned} 2020-04-22 20:46:14 +01:00