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114 commits 1 branch 0 tags 34 MiB
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14 commits

Author SHA1 Message Date
Tillmann Karras dacaeadb6a Raise SIGTRAP on non-Windows 2016-08-03 00:44:08 +01:00
MerryMage 64c17a2489 tests/FuzzArm: Print out IR upon failure 2016-08-02 13:48:06 +01:00
MerryMage 5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
Subv fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. 2016-07-18 16:13:33 -05:00
Subv 426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH. 
These tests do not test the behavior of writing to the PC.
 2016-07-18 16:13:02 -05:00
Subv c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. 2016-07-18 16:10:35 -05:00
MerryMage dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
MerryMage c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
Subv 0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00
MerryMage 866dce0f23 tests/Thumb: Add revsh (thumb) test 2016-07-16 19:22:57 +01:00
MerryMage 4b1c27e64f Implement arm_ADC_imm 2016-07-14 20:02:41 +01:00
MerryMage 07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage 8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage 65d27f3486 tests: Add some Arm tests 2016-07-12 09:12:56 +01:00