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Author SHA1 Message Date
Merry 39563c8ea8 Merged in bunnei/dynarmic (pull request #8) 
arm: Implement B/BL/BX instructions.
 2016-08-04 13:22:00 +01:00
bunnei 691e4139fa arm: Implement B/BL/BX instructions. 2016-08-03 16:49:01 -04:00
Tillmann Karras fc33f1d374 Implement more instructions 
SXTB, SXTH, SXTAB, SXTAH, UXTB, UXTH, UXTAB, UXTAH, REV16
 2016-08-03 00:47:17 +01:00
Tillmann Karras 30a90295b9 Implement data processing instructions 
ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORR, RSB, RSC, SBC, SUB,
TEQ, TST

The code could use some serious deduplication...
 2016-08-03 00:47:16 +01:00
Tillmann Karras fe71cc9d78 Disassemble reg-shifted regs in lower case 2016-08-03 00:47:16 +01:00
Tillmann Karras 2488926341 Add IR opcode RotateRightExtended 
to rotate through the carry flag
 2016-08-03 00:47:16 +01:00
Tillmann Karras dacaeadb6a Raise SIGTRAP on non-Windows 2016-08-03 00:44:08 +01:00
Tillmann Karras 306e070ab5 Use opcodes.inc for emit_x64.h 2016-08-03 00:44:08 +01:00
Tillmann Karras 61eddbd1fa Fix Linux build 2016-08-03 00:44:08 +01:00
MerryMage 1252bd653d RegAlloc: Define constructors for HostLocInfo to make MSVC happy 2016-08-03 00:25:42 +01:00
MerryMage a875c0c720 TranslateArm: Stub more ARM instructions 2016-08-02 21:59:33 +01:00
MerryMage 64c17a2489 tests/FuzzArm: Print out IR upon failure 2016-08-02 13:48:06 +01:00
MerryMage deb5e2c10d IR::DumpBlock: Incorrect use of std::map::at 2016-08-02 13:47:05 +01:00
MerryMage 4414ec5bc8 RegAlloc: Allow allocation of XMM registers 2016-08-02 13:46:12 +01:00
MerryMage 864081d1a0 BackendX64: ArithmeticShiftRight: Fix incorrect immediate size for SAR 2016-08-02 12:00:11 +01:00
MerryMage 6097a21955 TranslateArm: Reorganisation - Split visitor into multiple .cpp files 2016-08-02 11:54:04 +01:00
MerryMage 93af160c97 arm_types: Add FPSCR to Arm::LocationDescriptor and make Arm::LocationDescriptor have a FauxO-like interface 2016-08-02 11:54:02 +01:00
MerryMage be87038ffd IROpt: Port get/set elimination pass to current IR 2016-08-02 11:51:05 +01:00
MerryMage e60cea3a54 Add -pedantic-errors compilation flag 2016-08-01 19:54:31 +01:00
MerryMage cd86ef4236 Add -DBOOST_POOL_NO_MT as a compiler flag 2016-07-23 05:37:07 +01:00
MerryMage 51448aa06d More Speed 2016-07-22 23:55:00 +01:00
MerryMage 5fbfc6c155 Implement some simple IR optimizations (get/set eliminiation and DCE) 2016-07-21 21:48:45 +01:00
MerryMage 90d317b868 Implement memory endianness. Implement Thumb SETEND instruction. 2016-07-20 15:34:17 +01:00
MerryMage 98bd7ff6a5 Decoder/Thumb16: Remove BL{,X} prefix/suffix decoders. We have 32-bit thumb instruction support. 2016-07-20 12:08:17 +01:00
Merry 95316b8443 Merged in Subv/dynarmic/arm_mem_tests (pull request #4) 
Added some fuzz tests for most cases of ARM Load/Store instructions
 2016-07-20 10:19:55 +01:00
MerryMage 95588d3faa Fix Thumb BLX (imm), BL (imm) for negative immediates 2016-07-18 22:48:23 +01:00
MerryMage 3f11a149d7 Implement Thumb Instructions: BLX (imm), BL (imm) 2016-07-18 22:18:58 +01:00
Subv fce8f75077 Added a dummy (always fail) ARM test about Load/Store instructions that write to the PC. 2016-07-18 16:13:33 -05:00
Subv 426ffc9971 Added ARM fuzz tests for LDRD/LDR/LDRT/LDRB/LDRBT/LDRH and STRD/STR/STRT/STRB/STRBT/STRH. 
These tests do not test the behavior of writing to the PC.
 2016-07-18 16:13:02 -05:00
Subv c330d9e0e3 Increase the chance of generating instructions without conditions in the REV/REVSH/REV16 tests. 2016-07-18 16:10:35 -05:00
MerryMage e0d6e28b67 Implement Thumb instructions: BX, BLX (reg), B (T1), B (T2) 2016-07-18 21:04:39 +01:00
Subv ccc61472b9 Added format strings for ARM STRBT encodings A1 and A2 2016-07-18 14:20:58 -05:00
Subv 8617bf80a1 Added format strings for ARM LDRBT encodings A1 and A2 2016-07-18 14:18:39 -05:00
Subv 5d5ea9325c Added format strings for ARM STRT encodings A1 and A2 2016-07-18 14:05:53 -05:00
MerryMage 2363759c62 Implement thumb STM, LDM. Fix thumb POP implementation for P=1. 2016-07-18 20:05:35 +01:00
MerryMage 8a310777a1 backend/EmitX64: Handle new_pc<1:0> == '10' case in BXWritePC 2016-07-18 20:01:48 +01:00
Subv 77761ba032 Added the format strings for LDRT encodings A1 and A2. 2016-07-18 14:01:18 -05:00
MerryMage 14dcb18bbe Implemented Thumb Instructions: STR (imm, T1), STRB (imm), LDRB (imm), STR (imm, T2), LDR (imm, T2) 2016-07-18 18:48:08 +01:00
MerryMage a605a43ef9 Implement Thumb Instructions: STRH (imm), LDRH (imm) 2016-07-18 18:28:52 +01:00
MerryMage f9755870bb Implement Thumb Instructions: LDR (reg), LDRH (reg), LDRSH (reg), LDRB (reg), LDRSB (reg) 2016-07-18 18:02:02 +01:00
Merry 3b8790bf29 Merged in Subv/dynarmic/small_opt (pull request #3) 
Pass the current IR::Block by reference to the emitter.
 2016-07-18 17:38:12 +01:00
MerryMage dfef65d98f Implement thumb POP instruction 2016-07-18 17:37:48 +01:00
Subv 703a46ec99 Pass the current IR::Block by reference to the emitter. 
This avoids calling the copy constructor more times than needed.
 2016-07-18 11:27:33 -05:00
MerryMage f7e3d7b8d2 Implement Thumb PUSH instruction 2016-07-18 15:11:16 +01:00
MerryMage 9109b226af Implement Thumb instructions: ADD (SP plus imm, T1), ADD (SP plus imm, T2), SUB (SP minus imm) 2016-07-18 11:16:12 +01:00
MerryMage c18a3eeab4 Better MSVC support 
* Avoiding use of templated variables.
* Now compling on MSVC with /WX (warnings as errors).
* Fixed all MSVC warnings.
* Fixed MSVC source_groups.
 2016-07-18 10:38:22 +01:00
MerryMage bf99ddd065 Merge branch 'master' of MerryMageBitbucket:MerryMage/dynarmic 2016-07-18 10:33:52 +01:00
MerryMage 28a201da16 Implement Thumb ADR instruction 2016-07-18 09:25:33 +01:00
Merry 6708960aeb Merged in Subv/dynarmic/rev (pull request #2) 
Implemented ARM REV and REVSH instructions, with tests.
 2016-07-17 22:13:36 +01:00
Subv 0cdf5fe751 Implemented ARM REV and REVSH instructions, with tests. 2016-07-17 14:45:42 -05:00