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1347 commits 1 branch 0 tags 34 MiB
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48 commits

Author SHA1 Message Date
MerryMage 3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage 6918ef7360 microinstruction: Reorganize FPSCR related instruction queries 2020-04-22 20:46:22 +01:00
Lioncash a639fa5534 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() 
These were forgotten when the opcodes were added.
 2020-04-22 20:46:22 +01:00
Subv 4606a081c9 A64: The A64SetTPIDR IR instruction writes to a system register and should not be eliminated by the dead code elimination pass. 
Previously this instruction was alway eliminated, resulting in incorrect values for TPIDR_EL0.
 2020-04-22 20:46:21 +01:00
MerryMage e3da92024e A64: Implement system registers FPCR and FPSR 2020-04-22 20:46:15 +01:00
MerryMage b7a2c1a7df A64: Implement STXRB, STXRH, STXR, STLXRB, STLXRH, STLXR, LDXRB, LDXRH, LDXR, LDAXRB, LDAXRH, LDAXR 2020-04-22 20:46:14 +01:00
MerryMage bfd65bedfe A64: Implement DSB, DMB 2020-04-22 20:46:14 +01:00
MerryMage 5edd623b9d Implement DC instructions 2020-04-22 20:46:14 +01:00
MerryMage f378d2ef1b Forward declare IR::Opcode and IR::Type where possible 2020-04-22 20:46:14 +01:00
Lioncash 22632db337 microinstruction: Add ConditionalSelectNZCV opcode to ReadsFromCPSR()'s switch statement 2020-04-22 20:46:13 +01:00
MerryMage 6fc228f7fd ir_opt: Add A64 Get/Set Elimination Pass 2020-04-22 20:46:12 +01:00
MerryMage b513b2ef05 IR: Implement IR instructions A64{Get,Set}S 2020-04-22 20:44:38 +01:00
Lioncash 67443efb62 General: Convert multiple namespace specifiers to nested namespace specifiers where applicable 
Makes namespacing a little less noisy
 2020-04-22 20:44:38 +01:00
MerryMage 94383fd934 microinstruction: Missed A64{Read,Write}Memory128 from opcode information 2020-04-22 20:44:38 +01:00
MerryMage 394bd57bb6 microinstruction: bug: Add missing opcodes 2020-04-22 20:42:46 +01:00
MerryMage fff8e019dc reg_alloc: Consider bitwidth of data and registers when emitting instructions 2020-04-22 20:42:46 +01:00
MerryMage 0992987c98 A64: Add ExceptionRaised IR instruction 
The purpose of this instruction is to raise exceptions when certain decode-time
issues happen, instead of asserting at translate time. This allows us to
use the translator for code analysis without worrying about unnecessary asserts,
but also provides flexibility for the library user to perform custom behaviour
when one of these states are raised.
 2020-04-22 20:42:45 +01:00
MerryMage 25411da838 A32: Implement load stores (immediate) 2020-04-22 20:42:45 +01:00
MerryMage 68391b0a05 A64: Implement SVC 2020-04-22 20:42:45 +01:00
MerryMage cb481a3a48 A64: Implement compare and branch 2020-04-22 20:42:45 +01:00
MerryMage e8bcf72ee5 A64: PSTATE access and tests 2020-04-22 20:42:45 +01:00
MerryMage 23f3afe0b3 A64: Implement branch (register) 2020-04-22 20:42:45 +01:00
MerryMage 0641445e51 A64: Implement logical 2020-04-22 20:42:45 +01:00
MerryMage c09e69bb97 A64: Implement addsub instructions 2020-04-22 20:42:44 +01:00
MerryMage d1cef6ffb0 A64: Implement ADD_shifted 2020-04-22 20:42:44 +01:00
MerryMage 8bef20c24d IR: Split off A32 specific opcodes 2020-04-22 20:33:32 +01:00
MerryMage 19a7fb8992 jit_state: Split off CPSR.NZCV 2020-04-22 20:26:40 +01:00
MerryMage 7cac9519b0 microinstruction: Remove DecrementRemainingUses 2020-04-22 20:26:12 +01:00
MerryMage 523ae542f4 microinstruction: Implement HasAssociatedPseudoOperation 2017-04-04 13:10:50 +01:00
MerryMage 92a01b0cd8 Prefer ASSERT to DEBUG_ASSERT 2017-02-26 23:30:40 +00:00
MerryMage bbeea72eba ir_opt: Remove redundant shift instructions 2017-02-26 15:28:14 +00:00
MerryMage 4ed8ee7489 microinstruction: Void arguments when invalidating instruction 2017-02-18 21:29:23 +00:00
MerryMage 5f7ffe0d0b microinstruction: Implement Inst::AreAllArgsImmediates 2017-01-29 22:56:59 +00:00
MerryMage 22804dc6a5 microinstruction: Arguments of Inst::Use and Inst::UndoUse should be const 2017-01-29 22:53:46 +00:00
MerryMage 1d4446cad5 microinstruction: Removed unnecessary reference from argument of Inst::ReplaceUsesWith 2017-01-29 22:52:33 +00:00
MerryMage 48693eb6ff Implement coprocessor-related microinstructions 
* CoprocInternalOperation
* CoprocSendOneWord
* CoprocSendTwoWords
* CoprocGetOneWord
* CoprocGetTwoWords
* CoprocLoadWords
* CoprocStoreWords
 2017-01-08 14:56:06 +00:00
MerryMage 7cad6949e7 IR: Implement new pseudo-operation GetGEFromOp 2016-12-04 20:52:06 +00:00
MerryMage e166965f3e Implement VCMP 2016-12-03 11:41:09 +00:00
Mat M de1f831d79 microinstruction: Make use_count private (#53) 
Makes the operation a part of the direct interface.
 2016-11-30 21:51:06 +00:00
MerryMage b6f7b8babd ir: Implement GetGEFlags, SetGEFlags 2016-11-23 19:44:27 +00:00
MerryMage dca3b2f079 Implement VMRS and VMSR 2016-08-26 22:47:54 +01:00
MerryMage 4322c0907c microinstruction: Rename FindUseWithOpcode to GetAssociatedPseudoOperation, encapsulate associated variables 2016-08-25 21:08:47 +01:00
MerryMage e0f9dead5d microinstruction: Identity's type depends on the type of its argument 2016-08-23 15:48:30 +01:00
MerryMage 8d1b9f32ca Standardize indentation of switch statments 2016-08-23 12:19:27 +01:00
Lioncash 47f285249b microinstruction: Introduce convenience informational functions 
Whenever more rigorous optimizations are attempted (or even basic ones),
it's usually helpful to know what overall kind of instruction is being
dealt with, in the event certain classes of instructions may be eligible
for optimization.
 2016-08-22 21:36:48 +01:00
MerryMage 192a0029be ir/opcodes: Implement IR::AreTypesCompatible 
Type-checking is now occuring in more than one place.
 2016-08-19 01:34:14 +01:00
Lioncash 841098a0bc ir: separate components out a little more 2016-08-17 20:46:21 +01:00