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Author SHA1 Message Date
MerryMage 3874cb37e3 A64: Implement SQXTN (vector) 2020-04-22 20:46:22 +01:00
MerryMage 8ef114d48f emit_x64_vector: packusdw reqiures SSE4.1 
In EmitVectorSignedSaturatedNarrowToUnsigned32.
 2020-04-22 20:46:22 +01:00
MerryMage 712c6c1d7e A64: Implement SQSHRUN, SQRSHRUN (vector) 2020-04-22 20:46:22 +01:00
MerryMage c5722ec963 simd_shift_by_immediate: Simplify ShiftRight 2020-04-22 20:46:22 +01:00
MerryMage f020dbe4ed A64: Implement SQXTUN 2020-04-22 20:46:22 +01:00
MerryMage 6918ef7360 microinstruction: Reorganize FPSCR related instruction queries 2020-04-22 20:46:22 +01:00
Lioncash a639fa5534 microinstruction: Add missing FP scalar opcodes to ReadsFromFPSCR() and WritesToFPSCR() 
These were forgotten when the opcodes were added.
 2020-04-22 20:46:22 +01:00
Lioncash 3ca18d8a6d u128: Make Bit() a const-qualified member function 
This function doesn't modify the struct members, so it can be made
const.
 2020-04-22 20:46:22 +01:00
MerryMage b2e4c16ef8 A64: Implement FRSQRTS (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage 45dc5f74f3 A64: Implement FRSQRTE (vector), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage b74d5520f9 A64: Implement FRSQRTS (scalar), single/double variant 2020-04-22 20:46:22 +01:00
MerryMage 506e544bfe IR: Implement FPRSqrtStepFused 2020-04-22 20:46:22 +01:00
MerryMage 6eb069e80d fp: Implement FPRSqrtStepFused 2020-04-22 20:46:22 +01:00
MerryMage b0ff35fcd1 fp: Implement FPNeg 2020-04-22 20:46:22 +01:00
MerryMage ca6774ccce process_nan: Add two operand variant 2020-04-22 20:46:22 +01:00
Lioncash ace7d2ba50 A64: Implement FMAXP, FMINP, FMAXNMP and FMINNMP's scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
MerryMage 66bb05fc0a emit_x64_floating_point: Fixup special NaN case in FMA FPMulAdd implementation 2020-04-22 20:46:21 +01:00
Lioncash 070637e0f6 fp: Use a forward declaration in fused.h 
It's permissible to forward declare here, so we can do so and eliminate
a direct header dependency
 2020-04-22 20:46:21 +01:00
Lioncash 030820f649 u128: Implement comparison operators in terms of one another 
We can just implement the comparisons in terms of operator< and
implement inequality with the negation of operator==.
 2020-04-22 20:46:21 +01:00
MerryMage a04553eb91 tests: Print cpu info 2020-04-22 20:46:21 +01:00
MerryMage 76b07d6646 u128: StickyLogicalShiftRight requires special-casing for amount == 64 
In this case (128 - amount) == 64, and this invokes undefined behaviour
 2020-04-22 20:46:21 +01:00
Lioncash 49c7edf7c6 A64: Implement FMLA and FMLS (by element)'s double/single-precision scalar variant 2020-04-22 20:46:21 +01:00
Lioncash c704acafe4 A64: Implement FMUL (by element)'s scalar double/single-precision variant 2020-04-22 20:46:21 +01:00
MerryMage 0ce11b7b15 emit_x64_floating_point: Implement accurate fallback for FPMulAdd{32,64} 2020-04-22 20:46:21 +01:00
MerryMage e199887fbc fp: Implement FPMulAdd 2020-04-22 20:46:21 +01:00
MerryMage 53a8c15d12 process_nan: Add FPProcessNaNs3 2020-04-22 20:46:21 +01:00
MerryMage 1c8e93e74d block_of_code: Add SysV ABI fifth and sixth parameters 2020-04-22 20:46:21 +01:00
MerryMage 1fe8f51c54 u128: Add StickyLogicalShiftRight 2020-04-22 20:46:21 +01:00
MerryMage b0afd53ea7 u128: Add Multiply64To128 2020-04-22 20:46:21 +01:00
MerryMage 5566fab29a u128: Add u128::Bit 2020-04-22 20:46:21 +01:00
MerryMage 3e62fea003 u128: Add comparison operators 2020-04-22 20:46:21 +01:00
MerryMage f17cd6f2c5 unpacked: Use ResidualErrorOnRightShift in FPRoundBase 
Fixes a bug relating to exponents that are severely out of range.
 2020-04-22 20:46:21 +01:00
MerryMage 805428e35e fp: Remove MantissaT 2020-04-22 20:46:21 +01:00
MerryMage bda86fd167 FPRSqrtEstimate: Improve documentation of RecipSqrtEstimate 2020-04-22 20:46:21 +01:00
Lioncash 0a64a66b26 FPRSqrtEstimate: Deduplicate array bounds 
Dehardcodes a few constants in the loops.
 2020-04-22 20:46:21 +01:00
Lioncash b7bd70fd19 A64: Implement FMAXV, FMINV, FMAXNMV, and FMINNMV 2020-04-22 20:46:21 +01:00
Lioncash 664fb12e21 FPRSqrtEstimate: Use forward declarations where applicable 2020-04-22 20:46:21 +01:00
Lioncash 3447c82656 translate: Return by bool in helpers where applicable 
Gets rid of a bit of duplication regarding the early-out cases and makes
all helpers functions consistent (previously some had a return type of
bool, while others had a return type of void).
 2020-04-22 20:46:21 +01:00
Lioncash d65b056eba Simplify fallback case for EmitVectorSetElement64() 2020-04-22 20:46:21 +01:00
MerryMage 6087c2af6f emit_x64_floating_point: s/Esimate/Estimate/ 2020-04-22 20:46:21 +01:00
MerryMage f837ce8e78 simd_scalar_two_register_misc: Implement FRSQRTE, scalar variant 2020-04-22 20:46:21 +01:00
MerryMage bde58b04d4 IR: Implement FPRSqrtEstimate 2020-04-22 20:46:21 +01:00
MerryMage 16061c28f3 simd_vector_x_indexed_element: Implement FMUL (by element), vector variant 2020-04-22 20:46:21 +01:00
MerryMage 55eaa16615 a64_emit_x64: Ensure host has updated ticks in EmitA64GetCNTPCT 
Discovered by @Subv.
Fixes incomplete fix begun in 5a91c94dca47c9702dee20fbd5ae1f4c07eef9df.
That fix fails to take into account that LinkBlock doesn't update ticks until there
are no remaining ticks to be executed.

Test added to confirm fix.
 2020-04-22 20:46:21 +01:00
MerryMage edd795e991 a64_emit_x64: Fix stack misalignment on Windows for 128-bit exclusive writes 
Discovered by @Subv.
Includes a test to ensure this codepath is exercised on Windows.
 2020-04-22 20:46:21 +01:00
Lioncash 04b4c8b0cf emit_x64_aes: Eliminate extraneous usage of a scratch register in EmitAESInverseMixColumns() 
We can just use the same register the data is in as the result register,
eliminating the need to use a completely separate register to store the
result.
 2020-04-22 20:46:21 +01:00
Lioncash e5d80e998e A64: Implement SADDLV 2020-04-22 20:46:21 +01:00
Lioncash a1bc8ddb53 A64: Implement UADDLV 2020-04-22 20:46:21 +01:00
Lioncash 1dc1e3dcd8 fp: Use forward declarations where applicable 
Minimizes the amount of files that need to be rebuilt if the headers
ever change.
 2020-04-22 20:46:21 +01:00
Lioncash 46cb0d813b emit_x64_vector: Append 'v' prefix onto movq in AVX path 
This is something I missed when adding in the AVX broadcast code.
 2020-04-22 20:46:21 +01:00