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Author SHA1 Message Date
MerryMage 328422b740 RegAlloc: HostCall flushes all XMM regsiters 2016-08-07 21:02:16 +01:00
MerryMage 4dcd1d1859 Arm: BLX is UNPREDICTABLE when Rm is PC 2016-08-07 20:50:33 +01:00
MerryMage 1af5bef32c TranslateArm: Implement BLX (imm), BLX (reg) and BXJ 2016-08-07 20:40:31 +01:00
MerryMage 939bb5c0cb TranslateArm: Implement NOP 2016-08-07 20:08:31 +01:00
MerryMage e48df9d8fd TranslateArm: Implement Hint instructions as NOPs 2016-08-07 20:04:48 +01:00
MerryMage 3a465ba4a8 VFP: Implement VLDR 2016-08-07 19:59:35 +01:00
MerryMage a2c2db277b VFP: Implement VMOV (all variants) 2016-08-07 19:25:12 +01:00
MerryMage aba705f6b9 BackendX64: Merge Routines into BlockOfCode 2016-08-07 18:08:48 +01:00
MerryMage 0f412247ed VFP: Implement VSQRT 2016-08-07 12:19:07 +01:00
MerryMage cd8e7c0504 VFP: Implement VNEG 2016-08-07 12:04:21 +01:00
MerryMage da33af5abe VFP: Implement VMLA, VMLS, VNMLA, VNMLS 2016-08-07 11:49:06 +01:00
MerryMage 3f1345a1a5 VFP: Implement VNMUL, VDIV 2016-08-07 10:56:12 +01:00
MerryMage 12e7f2c359 VFP: Implement VMUL 2016-08-07 10:21:14 +01:00
MerryMage 97b5fa173f VFP: Implement VSUB 2016-08-07 01:45:52 +01:00
MerryMage ce6b5f8210 VFP: Implement VABS 2016-08-07 01:27:18 +01:00
MerryMage f88b1b4c2e FPSCR: Save and restore MSCSR across supervisor call, fix MXCSR exception mask 2016-08-07 01:10:19 +01:00
MerryMage c35f06470f VFP: Interpret VFP instructions when FPSCR.Len or FPSCR.Stride != 1 2016-08-06 23:01:18 +01:00
MerryMage 94b99f5949 Common: Add an intrusive list implementation; remove use of boost::intrusive::list. 2016-08-06 22:23:01 +01:00
Tillmann Karras 9264e2e04c Use XOR when loading a zero immediate 2016-08-06 21:17:11 +01:00
Tillmann Karras 55204a80d0 Implement SMMLA, SMMLS, SMMUL 2016-08-06 21:17:11 +01:00
Tillmann Karras 846d07d7b5 Add Sub64 opcode 2016-08-06 21:17:11 +01:00
Tillmann Karras b9f4f1ed0f Add carry support to MostSignificantWord 2016-08-06 21:17:11 +01:00
Tillmann Karras 01aebcb385 Remove *MulHi wrappers 2016-08-06 21:17:11 +01:00
Tillmann Karras 5e047107a0 Disassemble more instructions 
CLZ, SEL, USAD8, USADA8, SSAT, SSAT16, USAT, USAT16, SMLAL*, SMLA*,
SMUL*, SMLAW*, SMULW*, SMLAD, SMLALD, SMLSD, SMLSLD, SMUAD, SMUSD
 2016-08-06 21:17:11 +01:00
Tillmann Karras f99cb613cf Disassemble packs and more multiplies 2016-08-06 21:17:11 +01:00
Tillmann Karras 81d9d4b012 Add Subv's sign/zero extension tests 2016-08-06 21:17:11 +01:00
Tillmann Karras a281fcc744 Fix printf 2016-08-06 21:17:11 +01:00
MerryMage 7915f97d98 TranslateArm/LoadStore: Add default case to switches for arm_LDRD_imm and arm_LDRD_reg (fixes GCC warning) 2016-08-06 20:42:06 +01:00
MerryMage 4d127c19dd Common: Add a memory pool implementation, remove use of boost::pool 2016-08-06 20:41:00 +01:00
MerryMage 411e804b0d Interface: Forward declare Arm::LocationDescriptor 2016-08-06 20:11:35 +01:00
MerryMage 9ab7626374 Tests/VFP: Add tests for VADD.F32 2016-08-06 20:03:15 +01:00
MerryMage 4b31ea25a7 VFP: Implement VADD.{F32,F64} 2016-08-06 20:03:15 +01:00
MerryMage 8ff414ee0e Frontend/Decoder: 1. Remove member pointer as a template argument. 2. Sort ARM table such that unconditional instructions are on top. 2016-08-06 20:03:15 +01:00
MerryMage 94d5738f62 BackendX64/Routines: Add floating-point constants 2016-08-06 20:01:47 +01:00
MerryMage 8754728a82 BackendX64/RegAlloc: Corrected code emitted by EmitMove for XMM->Spill case 2016-08-06 20:01:47 +01:00
MerryMage 8cc4fe8a10 BackendX64/RegAlloc: HostLocToX64 now handles XMM registers properly 2016-08-06 20:01:47 +01:00
Merry cd1eef2801 Merged in bunnei/dynarmic/load_store (pull request #9) 
arm: Implement LDR/LDRB/LDRH/LDRD/STR/STRB/STRH/STRD.
 2016-08-06 14:22:45 +01:00
bunnei 2448d52394 load_store: Use correct types for LDR/STR. 2016-08-05 20:51:32 -04:00
bunnei 8c2300d477 arm: Implement LDRD reg/imm instructions. 2016-08-05 20:05:02 -04:00
bunnei 72608b7af6 arm: Handle Cond::NV (some 3DS games use this despite being obsolete). 2016-08-05 20:05:02 -04:00
bunnei ec3a98cf95 arm: Implement LDRH reg/imm instructions. 2016-08-05 20:05:01 -04:00
bunnei 192a0fba7a arm: Implement LDRB reg/imm instructions. 2016-08-05 20:05:00 -04:00
bunnei dfb318f208 arm: Implement STRD reg/imm instructions. 2016-08-05 20:04:59 -04:00
bunnei e931dc2496 arm: Implement STRH reg/imm instructions. 2016-08-05 20:04:58 -04:00
bunnei 9f77662b24 arm: Implement STRB reg/imm instructions. 2016-08-05 20:04:57 -04:00
bunnei a5e2116e12 fuzz_arm: Log write records on failure. 2016-08-05 20:04:57 -04:00
bunnei caab1bbc7c arm: Implement STR reg/imm instructions. 2016-08-05 20:04:56 -04:00
bunnei b09ecb4532 arm: Implement LDR reg/imm instructions. 2016-08-05 20:04:55 -04:00
MerryMage 856298577d EmitX64: Don't give MOVSX or MOVZX an immediate oparg 2016-08-06 01:03:39 +01:00
MerryMage 640ce48baa VFP: Implement {Get,Set}ExtendedRegister{32,64} 2016-08-05 19:06:10 +01:00