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Author SHA1 Message Date
MerryMage 28a201da16 Implement Thumb ADR instruction 2016-07-18 09:25:33 +01:00
Merry 24aa24b1bc Merged in Subv/dynarmic (pull request #1) 
Implemented ARM CMP (imm) instruction.
 2016-07-17 19:43:49 +01:00
Subv 7f09510945 Implemented ARM CMP (imm) instruction. 2016-07-17 13:29:37 -05:00
MerryMage 3720da4e19 Implement thumb16_{SXTH,SXTB,UXTH,UXTB,REV,REV16,REVSH} 2016-07-16 19:23:42 +01:00
MerryMage 866dce0f23 tests/Thumb: Add revsh (thumb) test 2016-07-16 19:22:57 +01:00
MerryMage 22b1bd7cc7 tests/Skyeye: Fix thumb REVSH translation 2016-07-16 19:22:09 +01:00
MerryMage 3ef9da9a92 Docs: Design documentation 2016-07-15 16:47:13 +01:00
MerryMage 4b1c27e64f Implement arm_ADC_imm 2016-07-14 20:02:41 +01:00
MerryMage 63242924fc Implement thumb16_SVC 2016-07-14 15:01:30 +01:00
MerryMage 181f78f36e Common: Remove src/common/logging/log.* 2016-07-14 14:55:08 +01:00
MerryMage 07eaf100ba Reorganise src/frontend: Add subdirectories disassembler and translate 2016-07-14 14:39:43 +01:00
MerryMage 9b2aff166a Implement arm_SVC 2016-07-14 14:29:46 +01:00
MerryMage 672ffb93d0 frontend/translator: Skeleton for Arm translator 2016-07-14 13:28:20 +01:00
MerryMage 7d7751c157 Allow IR blocks to require a cond for block entry. 
* IR: Add cond, cond_failed.
* backend_x64/EmitX64: Implement EmitCondPrelude
 2016-07-14 12:52:53 +01:00
MerryMage 4ab4ca58f9 backend_x64/EmitX64: Improve emitted code for non-carry ArithmeticShiftRight 2016-07-14 09:02:27 +01:00
MerryMage 08e848044d backend_x64: Inline Routines::GenReturnFromRunCode into emitted code 2016-07-12 16:46:27 +01:00
MerryMage 619b451902 clang support 2016-07-12 14:31:43 +01:00
MerryMage 8449deb0bc MSVC support 2016-07-12 13:28:09 +01:00
MerryMage 44352680c6 s/thumb1/thumb16/g: Thumb16 refers to 16-bit thumb instructions, and Thumb32 to 32-bit ones 2016-07-12 11:09:34 +01:00
MerryMage 6e46e7899a Translate/Thumb: Fallback to interpreter for Thumb32 instructions 2016-07-12 11:02:45 +01:00
MerryMage 60455f9bbc tests/fuzz_thumb: Fuzz instructions that may change the PC 2016-07-12 10:58:57 +01:00
MerryMage 09420d190b IR: Implement IR microinstructions ALUWritePC and LoadWritePC 2016-07-12 10:58:14 +01:00
MerryMage 65d27f3486 tests: Add some Arm tests 2016-07-12 09:12:56 +01:00
MerryMage f85b86486b frontend/TranslateArm: Just interpret all ARM instructions 2016-07-12 09:11:35 +01:00
MerryMage 1410221b47 Implement thumb1_STR_reg, thumb1_STRH_reg, thumb1_STRB_reg 2016-07-11 23:11:05 +01:00
MerryMage e7922e4fef Implement thumb1_LDR_literal, thumb1_LDR_imm_t1 2016-07-11 22:43:53 +01:00
MerryMage cbcf61a9e6 backend_x64/RegAlloc: Provide convenience function HostCall to save registers necessary as per host ABI 2016-07-11 15:28:10 +01:00
MerryMage d92a771e3c tests/fuzz_thumb: Implement verification of memory writes 2016-07-10 13:29:15 +08:00
MerryMage f0f14fa5e8 Implement thumb1_MOV_reg 2016-07-10 13:10:06 +08:00
MerryMage 8920ce79b9 Implement thumb_CMP_reg_t2 2016-07-10 12:23:16 +08:00
MerryMage 3f7290db16 tests/fuzz_thumb: Change how test instructions are generated (Introduce InstructionGenerator struct) 2016-07-10 12:17:02 +08:00
MerryMage ac2fb6b925 Implement thumb1_MVN_reg 2016-07-10 10:49:01 +08:00
MerryMage d11df9067d Implement thumb1_BIC_reg 2016-07-10 10:44:45 +08:00
MerryMage 98a64a92b1 Implement thumb1_ORR_reg 2016-07-10 09:06:38 +08:00
MerryMage 3fe46d2c6f Implement thumb1_CMN_reg 2016-07-10 08:55:56 +08:00
MerryMage 641dbf8eb4 Implement thumb1_CMP_reg 2016-07-10 08:52:28 +08:00
MerryMage 46408267c3 Implement thumb1_RSB_imm 2016-07-10 08:44:07 +08:00
MerryMage 6536ad9618 Implement thumb1_TST_reg 2016-07-10 08:35:58 +08:00
MerryMage 8145b33882 Implemented thumb1_ROR_reg 2016-07-10 08:18:17 +08:00
MerryMage 207cb74dc9 Implement thumb1_SBC_reg 2016-07-09 08:27:41 +08:00
MerryMage 1953e44532 Implement thumb1_ADC_reg 2016-07-08 22:17:39 +08:00
MerryMage 9e9fa62d5f Implement thumb1_SUB_imm_t2 2016-07-08 21:48:55 +08:00
MerryMage 0a1f153805 tests/fuzz_thumb: Don't poison memory as that slows down tests tremendously 2016-07-08 21:43:28 +08:00
MerryMage 8c587df8ce Implement thumb1_ADD_imm_t2 2016-07-08 21:38:43 +08:00
MerryMage aa72323823 Implement thumb1_CMP_imm 2016-07-08 21:32:01 +08:00
MerryMage 98f300144b Implement thumb1_MOV_imm 2016-07-08 21:27:27 +08:00
MerryMage 34be20e4d6 Implement thumb1_SUB_imm 2016-07-08 20:57:53 +08:00
MerryMage a2e40eb922 Implement thumb1_ADD_imm 2016-07-08 19:15:30 +08:00
MerryMage 92142d5a22 Implement thumb1_SUB_reg 2016-07-08 18:49:30 +08:00
MerryMage df0c324923 Implement thumb1_EOR_reg 2016-07-08 18:14:54 +08:00