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Author SHA1 Message Date
Merry 22d87bcbe5 emit_arm64_a32: Implement A32SetGEFlagsCompressed 2022-10-18 15:04:30 +01:00
Merry 735f5b787a emit_arm64_a32: Fix A32SetCpsrNZC for immediate carry 2022-10-18 15:04:30 +01:00
Merry 33b3376fb1 emit_arm64_a32: Implement A32SetCpsrNZCVRaw, A32SetCpsrNZCVQ 2022-10-18 15:04:30 +01:00
Merry 11b665c027 emit_arm64_a32: Implement A32SetCpsr (temporary implementation) 2022-10-18 15:04:30 +01:00
Merry 950400fb6b arm64/a32_jitstate: Adjust structure 2022-10-18 15:04:30 +01:00
Merry 726e116e28 emit_arm64_saturation: Implement SignedSaturatedAddWithFlag32 2022-10-18 15:04:30 +01:00
Merry babfb7d7b8 IR/saturation: Revamp saturated add/sub IR instructions 2022-10-18 15:04:30 +01:00
Merry 2d0bf7ca9b emit_arm64_data_processing: Implement overflow output for Add 2022-10-18 15:04:30 +01:00
Merry adb18fd0a7 emit_arm64_data_processing: Implement LogicalShift{Left,Right}64 2022-10-18 15:04:30 +01:00
Merry 0692f1d40e emit_arm64_data_processing: EmitAddSub: Handle zero immediate w/ flag output 2022-10-18 15:04:30 +01:00
Merry cd537dc711 IR: Rename PackedAbsDiffSumS8 to PackedAbsDiffSumU8 2022-10-18 15:04:30 +01:00
Merry ee2bc92993 emit_arm64_saturation: Implement SignedSaturation 2022-10-18 15:04:30 +01:00
Merry e73c390927 emit_arm64_packed: Fix signed packed add sub 2022-10-18 15:04:30 +01:00
Merry c8b3be5512 emit_arm64_data_processing: Implement Div 2022-10-18 15:04:30 +01:00
Merry a320a333e1 emit_arm64_packed: Implement PackedAbsDiffSumS8 2022-10-18 15:04:30 +01:00
Merry 0ebbc4a9c5 emit_arm64_packed: Implement PackedSelect 2022-10-18 15:04:30 +01:00
Merry ac7908164a emit_arm64_packed: Implement packed halving operations 2022-10-18 15:04:30 +01:00
Merry d1909c5efb emit_arm64_packed: Implement halving add sub exchange 2022-10-18 15:04:30 +01:00
Merry ff34f4c6ae emit_arm64_data_processing: Fix flag reading in AddSub 
Also improve codegen for ZR case.
 2022-10-18 15:04:30 +01:00
Merry aaa0773695 emit_arm64_data_processing: Add carry output to MostSignificantWord 2022-10-18 15:04:30 +01:00
Merry 5c54c7d968 emit_arm64_packed: Implement packed add sub exchange 2022-10-18 15:04:30 +01:00
Merry 0bd7601844 emit_arm64_packed: Implement PackedSubU16 2022-10-18 15:04:30 +01:00
Merry 1810bd6547 emit_arm64_packed: Implement PackedSubU16 2022-10-18 15:04:30 +01:00
Merry fb6ac45259 emit_arm64_packed: Implement PackedSubS8 2022-10-18 15:04:30 +01:00
Merry 2076495d9e emit_arm64_packed: Implement PackedSubU8 2022-10-18 15:04:30 +01:00
Merry 0b53290dd7 emit_arm64_a32: Implement A32GetCpsr 2022-10-18 15:04:30 +01:00
Merry 8a0359ec52 emit_arm64_a32: Implement barriers 2022-10-18 15:04:30 +01:00
Merry a7f675864b emit_arm64_packed: Implement all saturated packed operations 2022-10-18 15:04:30 +01:00
Merry 7aeaa46a0b emit_arm64_packed: Implement PackedAddS16 2022-10-18 15:04:30 +01:00
Merry 66858c99b8 emit_arm64_packed: Implement PackedAddU16 2022-10-18 15:04:30 +01:00
Merry 179137be5a emit_arm64_saturation: Implement UnsignedSaturation 2022-10-18 15:04:30 +01:00
Merry 02d3a5a242 emit_arm64_a32: Implement A32OrQFlag 2022-10-18 15:04:30 +01:00
Merry a50eb6cf34 emit_arm64_packed: Implement PackedAddS8 2022-10-18 15:04:30 +01:00
Merry 619adce84f emit_arm64_packed: Implement PackedAddU8 2022-10-18 15:04:30 +01:00
Merry 8f1f1c8f0b emit_arm64_packed: Implement {Get,Set}GEFlags 2022-10-18 15:04:30 +01:00
Merry 2dce8ea5a8 emit_arm64_data_processing: Fix MostSignificantWord 2022-10-18 15:04:30 +01:00
Merry 9b09acee47 oaknut: Implement arranged accessors from DReg and QReg 2022-10-18 15:04:30 +01:00
Merry 3d420e34ae emit_arm64_data_processing: Fix LogicalShiftRight32 for immediate shift = 32 2022-10-18 15:04:30 +01:00
Merry 78e266a869 test_generator: Increase iterations 2022-10-18 15:04:30 +01:00
Merry a5f3164c38 backend/arm64/reg_alloc: Handle immediates in DefineAsExisting 2022-10-18 15:04:30 +01:00
Merry 277f7a76e9 arm64: Stub PushRSB 2022-10-18 15:04:30 +01:00
Merry ef137dd8b9 emit_arm64_data_processing: Correct ArithmeticShiftRight32 2022-10-18 15:04:30 +01:00
Merry 70d9137859 backend/arm64/reg_alloc: Handle immediates in PrepareForCall 2022-10-18 15:04:30 +01:00
Merry 187f89951d emit_arm64_data_processing: Implement Mul 2022-10-18 15:04:30 +01:00
Merry bf55920ce9 backend/arm64/reg_alloc: Support multiple locks on a location 2022-10-18 15:04:30 +01:00
Merry 6bcfaee1f4 emit_arm64_data_processing: Implement LogicalShiftRight32 2022-10-18 15:04:30 +01:00
Merry 7840caef6e emit_arm64_data_processing: Fix bug in EmitBitOp 2022-10-18 15:04:30 +01:00
Merry 02cfbb8b0b backend/arm64/reg_alloc: Generate immediates when required 2022-10-18 15:04:30 +01:00
Merry bdb41be0c5 emit_arm64_data_processing: Implement ZeroExtend 2022-10-18 15:04:30 +01:00
Merry 7ed217ff77 emit_arm64_data_processing: Implement SignExtend 2022-10-18 15:04:30 +01:00