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Author SHA1 Message Date
Wunkolo fbc306f702 [a64] Implement multi-arch capstone support 2024-06-23 14:00:24 -07:00
Wunkolo 6e83e2a42d [a64] Fix instruction constant generation 
Fixes some offset generation as well
 2024-06-23 14:00:24 -07:00
Wunkolo dc6666d4d2 [a64] Update guest calling conventions 
Guest-function calls will use W17 for indirect calls
 2024-06-23 14:00:24 -07:00
Wunkolo fd32c0e959 [a64] Fix 32-bit store 
You wouldn't believe how much time this bug costed me
 2024-06-23 14:00:24 -07:00
Wunkolo 2d093ae4ba [a64] Use offsetof to reload membase 2024-06-23 14:00:24 -07:00
Wunkolo 47665fddb8 [a64] Compute memory offsets as 32-bit registers 
Additionally fixes some instruction forms to use the more general `STR` instruction with an offset
 2024-06-23 14:00:24 -07:00
Wunkolo b18f2fffff [a64] Fix up-casting zero/sign extensions 2024-06-23 14:00:24 -07:00
Wunkolo c6a7270a06 [a64] Fix external function call arguments 
`x0` was loading the thunk rather than using `xip`

Fixes lots of init bugs!
 2024-06-23 14:00:24 -07:00
Wunkolo e4d3b2a484 [a64] Increase function code size to 1MiB 2024-06-23 14:00:24 -07:00
Wunkolo ba924feea5 [a64] Fix immediates being too large 
These instructions need to use an extra register to generate their constants if they are too large
 2024-06-23 14:00:24 -07:00
Wunkolo 540344fd27 [a64] Fix EmitGetCurrentThreadId type 
16-bit word rather than 8-bit
 2024-06-23 14:00:24 -07:00
Wunkolo 906d0c6590 [a64] Remove standard prolog/epilog from thunks 
Fixes callstacks!!!!
 2024-06-23 14:00:24 -07:00
Wunkolo 49f9edbfab [a64] Reorganize guest register allocation 
Share a somewhat similar calling convention as ARM64
 2024-06-23 14:00:24 -07:00
Wunkolo 0f9769baac [a64] Refactor REV{16,32} to REV 
Derive the reversal-size from the register-size.
REV32 is also the wrong one to be using here since it will reverse the bytes of upper and lower 32-bit words.
 2024-06-23 14:00:24 -07:00
Wunkolo 52b259369e [a64] Fix ComputeMemoryAddress{Offset} register stomp 
`W1` is a possible HIR register allocation and using W1 here was stomping over it. Don't use W1, use the provided "scratch" register.
 2024-06-23 14:00:24 -07:00
Wunkolo 647d26c20a [a64] Implement OPCODE_ATOMIC_COMPARE_EXCHANGE 2024-06-23 14:00:24 -07:00
Wunkolo cf6c2c2aee [a64] Implement OPCODE_ATOMIC_EXCHANGE 2024-06-23 14:00:23 -07:00
Wunkolo d656c5b462 [a64] Implement OPCODE_{LOAD,STORE}_LOCAL 2024-06-23 14:00:23 -07:00
Wunkolo 8a1e343c3b [a64] Implement OPCODE_MEMORY_BARRIER 2024-06-23 14:00:23 -07:00
Wunkolo 8836eb2892 [a64] Implement OPCODE_MEMSET 2024-06-23 14:00:23 -07:00
Wunkolo 4f5c640f3c [a64] Refactor REV{32,64} to REV 
Let the register type determine the reverse-size

REV32 was also the wrong instruction to use.
 2024-06-23 14:00:23 -07:00
Wunkolo 2b3147b2ed [a64] Fix CallIndirect return address 
Should be `GUEST_RET_ADDR` not `GUEST_CALL_RET_ADDR`.
 2024-06-23 14:00:23 -07:00
Wunkolo 8b4b713e0e [a64] Remove redundant zero-extension during address computation 
Also changes the register to X3 by default
 2024-06-23 14:00:23 -07:00
Wunkolo 018e484d6b [a64] Implement OPCODE_{LOAD,STORE}_MMIO 2024-06-23 14:00:23 -07:00
Wunkolo b5d55e1464 [a64] Refactor XSP to SP 2024-06-23 14:00:23 -07:00
Wunkolo 5bff71f143 [a64] Fix emitted function prolog/epilog 2024-06-23 14:00:23 -07:00
Wunkolo 6a5f4611e2 [a64] Update Membase and Context register 2024-06-23 14:00:23 -07:00
Wunkolo c428d79e18 [a64] Refactor thunk prolog/epilog 2024-06-23 14:00:23 -07:00
Wunkolo 9ec4b68cae [a64] Optimize Volatile/NonVolatile push/pop 2024-06-23 14:00:23 -07:00
Wunkolo 17987ca755 [a64] Use X4 for address-generation veneer 2024-06-23 14:00:23 -07:00
Wunkolo 9b70ea07ef [a64] Draft Windows-ARM64 stack unwinding data 
Things still get weird at the thunks, but this allows for callstacks between-to-guest calls
 2024-06-23 14:00:23 -07:00
Wunkolo a1741bf609 [a64] Pad code cache with 0x00 bytes 2024-06-23 14:00:23 -07:00
Wunkolo dfa5bdbafb [a64] Fix ResolveFunctionThunk call 
Resolving the function puts it into X0 and should be called immediately after.

We were just calling ResolveFunction on ResolveFunction recursively
 2024-06-23 14:00:23 -07:00
Wunkolo 65288d5796 [a64] Fix resetting of labels during Emplace 
On the x64 side, this is the same as the `reset()` function resetting the label-manager
 2024-06-23 14:00:23 -07:00
Wunkolo 5b8ac36aa6 [a64] Fix ResolveFunction thunk 
Register was getting stomped over
 2024-06-23 14:00:23 -07:00
Wunkolo 725ea3d08c [a64] Implement control sequences 
Implements control sequences such as conditional branching, breaking, and trapping
 2024-06-23 14:00:23 -07:00
Wunkolo 8257740d21 [a64] Implement HIR Branch labeling 
Adds support for HIR labels to create actual oaknut labels
 2024-06-23 14:00:23 -07:00
Wunkolo e5fd3d340c [a64] Implement OPCODE_PACK(SHORT) 
Fails unit tests due to subtle rounding errors

`SHORT_4` unit-test is missing but implementation is the same as `SHORT_4`
 2024-06-23 14:00:23 -07:00
Wunkolo 3b2612bfc0 [a64] Implement OPCODE_PACK(FLOAT16) 
Fails the unit tests due to subtle rounding errors
 2024-06-23 14:00:23 -07:00
Wunkolo e62f3f31d4 [a64] Fix native vector calls 
Arguments need to be pointers stored in X0, X1, X2, ... rather than bassed directly in Q0, Q1 etc.

There are no unit tests for these functions in particular.
 2024-06-23 14:00:23 -07:00
Wunkolo 35e8a809b1 [a64] Implement OPCODE_VECTOR_ADD 
There is quite literally an instruction for each and every one of these cases.

Passes unit tests
 2024-06-23 14:00:23 -07:00
Wunkolo 584c34cbd6 [a64] Implement OPCODE_VECTOR_MAX 
Passes unit tests
 2024-06-23 14:00:22 -07:00
Wunkolo ebd1f84d25 [a64] Implement OPCODE_VECTOR_MIN 
Passes unit tests
 2024-06-23 14:00:22 -07:00
Wunkolo 3ac51212a6 [a64] Implement OPCODE_VECTOR_ROTATE_LEFT 
Uses the emulated fallback for now. Will have to come back to this later. Passes unit tests.
 2024-06-23 14:00:22 -07:00
Wunkolo 7feea4c60c [a64] Implement OPCODE_VECTOR_{SHR,SHA} 
Passes all unit tests
 2024-06-23 14:00:22 -07:00
Wunkolo 88ed113541 [a64] Remove volatile storing of X0/Q0 
We dont load it back so no need to store it
 2024-06-23 14:00:22 -07:00
Wunkolo 07a4df8e2f [a64] Implement OPCODE_VECTOR_SHL 
Vector registers are passed as pointers rather than directly in the `Qn` registers. So these functions should be taking pointer-type arguments rather than vector-register types directly.

Fixes `OPCODE_VECTOR_SHL` and passes unit tests.
 2024-06-23 14:00:22 -07:00
Wunkolo 3d345d71a7 [a64] Fix overwriting of return-value registers 
These are stomping over X0 and Q0 which is returning input argument registers as return values.
Fixes some guest-to-host calls.
 2024-06-23 14:00:22 -07:00
Wunkolo 6a0e6a9ca9 [a64] Fix indirect and external calls 2024-06-23 14:00:22 -07:00
Wunkolo 8aa4b9372a [a64] Fix memory address generation 2024-06-23 14:00:22 -07:00