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Author SHA1 Message Date
Wunkolo 35e8a809b1 [a64] Implement OPCODE_VECTOR_ADD 
There is quite literally an instruction for each and every one of these cases.

Passes unit tests
 2024-06-23 14:00:23 -07:00
Wunkolo 584c34cbd6 [a64] Implement OPCODE_VECTOR_MAX 
Passes unit tests
 2024-06-23 14:00:22 -07:00
Wunkolo ebd1f84d25 [a64] Implement OPCODE_VECTOR_MIN 
Passes unit tests
 2024-06-23 14:00:22 -07:00
Wunkolo 3ac51212a6 [a64] Implement OPCODE_VECTOR_ROTATE_LEFT 
Uses the emulated fallback for now. Will have to come back to this later. Passes unit tests.
 2024-06-23 14:00:22 -07:00
Wunkolo 7feea4c60c [a64] Implement OPCODE_VECTOR_{SHR,SHA} 
Passes all unit tests
 2024-06-23 14:00:22 -07:00
Wunkolo 88ed113541 [a64] Remove volatile storing of X0/Q0 
We dont load it back so no need to store it
 2024-06-23 14:00:22 -07:00
Wunkolo 07a4df8e2f [a64] Implement OPCODE_VECTOR_SHL 
Vector registers are passed as pointers rather than directly in the `Qn` registers. So these functions should be taking pointer-type arguments rather than vector-register types directly.

Fixes `OPCODE_VECTOR_SHL` and passes unit tests.
 2024-06-23 14:00:22 -07:00
Wunkolo 3d345d71a7 [a64] Fix overwriting of return-value registers 
These are stomping over X0 and Q0 which is returning input argument registers as return values.
Fixes some guest-to-host calls.
 2024-06-23 14:00:22 -07:00
Wunkolo 6a0e6a9ca9 [a64] Fix indirect and external calls 2024-06-23 14:00:22 -07:00
Wunkolo 8aa4b9372a [a64] Fix memory address generation 2024-06-23 14:00:22 -07:00
Wunkolo 124f684987 [a64] Fix Guest-To-Host native calls 
These calls need to preserve and restore the `lr` register.

Unit tests all run now!
 2024-06-23 14:00:22 -07:00
Wunkolo defb68eae2 [a64] Fix StackLayout 
Wrong register index and vector-register size
 2024-06-23 14:00:22 -07:00
Wunkolo 10cba8e166 [a64] Implement OPCODE_{SHR,SHA} 2024-06-23 14:00:22 -07:00
Wunkolo 67706824c6 [a64] Implement OPCODE_VECTOR_SHA 2024-06-23 14:00:22 -07:00
Wunkolo 72380bf833 [a64] Implement OPCODE_PACK(D3DCOLOR) 2024-06-23 14:00:22 -07:00
Wunkolo 1b574be0e6 [a64] Implement OPCODE_LOAD_VECTOR_SHR 2024-06-23 14:00:22 -07:00
Wunkolo 61feb6af74 [a64] Implement OPCODE_LOAD_VECTOR_SHL 2024-06-23 14:00:22 -07:00
Wunkolo 10310d7e2f [a64] Implement OPCODE_INSERT 2024-06-23 14:00:22 -07:00
Wunkolo 652b7a1370 [a64] Implement OPCODE_SPLAT 2024-06-23 14:00:22 -07:00
Wunkolo b9571cfda0 [a64] Implement OPCODE_EXTRACT 2024-06-23 14:00:22 -07:00
Wunkolo 39429aada7 [a64] Fix BYTE_SWAP_V128 
This just reverses the bytes of 32-bit values, not reverse the whole vector.
 2024-06-23 14:00:22 -07:00
Wunkolo 9960ef9deb [CPU] Implement ARM64 CPU backend 
First pass framework that gets emitted ARM code executing.

Based on the x64 backend, implements an ARM64 JIT backend.
 2024-06-23 14:00:22 -07:00
Wunkolo 2284ed417a [Base] Add ARM64 utility functions 
Mostly element-accessors
 2024-06-23 14:00:22 -07:00
Wunkolo 59bc265941 [a64] Integrate oaknut submodule 
Header-only library for emitting arm64v8 instructions.

Enables C++20 only for the a64 backend for now
 2024-06-23 14:00:22 -07:00
Wunkolo ffc966c9ea [CPU] Add ARM64 backend build target 
Adds the new `xenia-cpu-backend-a64` build-target with linkage following the x64 backend.
 2024-06-23 14:00:21 -07:00
Wunkolo a0f6cd7a49 [Build] Link SDL2 to xenia-app 
Addresses a build issue that seems to occur now that xenia-app is not
getting SDL2 through one of its submodues
 2024-06-23 13:48:17 -07:00
Wunkolo aa4a3e09e4 [UI] Fix divide-by-zero hazard 
This value is currently returning `0` on ARM machines and throws an exception.
 2024-04-28 19:09:28 -07:00
Wunkolo f2b05ead9d [CPU] Stub ARM64 to Null CPU backend 
Adding the `a64` backend will be a different PR. For now it's stubbed to
the null backend to allow the main executable to open without failing
initalization.
 2024-04-28 18:55:28 -07:00
Wunkolo 045441a305 [Base] Add Windows-ARM64 bit_count implementation 
Uses intrinsics from https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-170
 2024-04-27 17:49:40 -07:00
Wunkolo fe9c98efac [CPU] Disable x64 backend on ARM64 2024-04-27 17:43:10 -07:00
Wunkolo f25484854c [Base] Disable AVX check on ARM64 2024-04-27 17:29:06 -07:00
Wunkolo b48ec84b3c [ImGui] Stub ARM64 host debug text 
Marked as TODO for now
 2024-04-27 17:26:42 -07:00
Wunkolo 1874f0c72f [CPU] Add Windows ARM64 stack-walker 2024-04-27 17:15:53 -07:00
Wunkolo a6d9113b21 [Base] Add Windows-ARM64 exception handling 2024-04-27 17:10:31 -07:00
Wunkolo 17461771ae [Build] Add Windows ARM64 support 
Separates the `Windows` platform into `Windows-x86_64` and
`Windows-ARM64`. Adds `--arch` argument to `build`.
Removes x64 backend on non-x64 targets.
 2024-04-27 16:45:46 -07:00
Gliniak f6b5424a9f [VFS] Fixed invalid month decoding in decode_fat_timestamp 2023-09-14 12:32:51 +03:00
Gliniak 0f331b5313 [Testing] Added test project for vfs 
- Added test case for: decode_fat_timestamp
- Changed location of: decode_fat_timestamp
 2023-09-14 12:32:51 +03:00
Gliniak c5e6352c34 [CPU] Added constant propagation pass for: OPCODE_AND_NOT 2023-07-27 23:41:45 +03:00
Adriano Martins 1887ea0795 [Base] Add missing #include <cstdint> to utf8.cc 2023-07-27 13:02:54 +03:00
Gliniak 00aba94b98 [NET] NetDll___WSAFDIsSet: Fixed incorrect endianness of fd_count 
Plus: limit it to 64 entries
Thanks to Bo98 for pointing that out
 2023-06-09 19:47:56 -05:00
Roy Stewart 07e81fe172 [Base] Filter out relative directories on linux 2023-06-09 19:47:28 -05:00
Roy Stewart 41c423109f [Base] Set the path for posix file info 2023-06-09 19:43:49 -05:00
Adrian 4a3b04d4ee [XAM] Implemented XamGetCurrentTitleId 2023-06-09 19:43:15 -05:00
Gliniak 858af5ae75 [XAM] xeXamContentCreate - Disposition cleanup 2023-06-09 19:42:48 -05:00
Gliniak e110527bfe [Base] ListFiles: Prevent leakage of file descriptors 2023-06-09 19:41:27 -05:00
Wunkolo 6ee2e3718f [x64] Add AVX512 optimizations for OPCODE_VECTOR_COMPARE_UGT(Integer) 
AVX512 has native unsigned integer comparisons instructions, removing
the need to XOR the most-significant-bit with a constant in memory to
use the signed comparison instructions. These instructions only write to
a k-mask register though and need an additional call to `vpmovm2*` to
turn the mask-register into a vector-mask register.

As of Icelake:
`vpcmpu*` is all L3/T1
`vpmovm2d` is L1/T0.33
`vpmovm2{b,w}` is L3/T0.33

As of Zen4:
`vpcmpu*` is all L3/T0.50
`vpmovm2*` is all L1/T0.25
 2023-05-29 14:57:09 -05:00
Wunkolo 121bf93cbe [PPC] Implement vsubcuw 
Other half of #2125. I don't know of any title that utilizes this instruction, but I went ahead and implemented it for completeness.

Verified the implementation with `instr__gen_vsubcuw` from #1348. Can be grabbed with:
```
git checkout origin/gen_tests -- src\xenia\cpu\ppc\testing\*vsubcuw.s
```
 2023-05-29 14:56:12 -05:00
Wunkolo 93b77fb775 [PPC] Implement vaddcuw 
I don't know of any title that utilizes this instruction, but I went
ahead and implemented it for completeness.

Verified the implementation with `instr__gen_vaddcuw` from #1348. Can be
grabbed with:
```
git checkout origin/gen_tests -- src\xenia\cpu\ppc\testing\*vaddcuw.s
```
 2023-05-29 14:56:00 -05:00
Triang3l ed64e3072b [GPU] Remove implicit bool cast in memexport checks 2023-05-05 21:38:45 +03:00
Triang3l 0e81293b02 [GPU] Remove a dangerous comment about break after exece [ci skip] 
There can be jumps across an exece, so the code beyond it may still be
executed.
 2023-05-05 21:32:02 +03:00