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https://github.com/xenia-project/xenia.git
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[Testing] Add missing avg and min/max tests
This commit is contained in:
Herman S.
parent
3461f2578b
commit
4c7d152fee
18 changed files with 698 additions and 9 deletions
44
src/xenia/cpu/ppc/testing/instr_vavgsb.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vavgsb.s
Normal file
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@ -0,0 +1,44 @@
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test_vavgsb_1:
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#_ REGISTER_IN v3 [02040608, 0A0C0E10, 12141618, 1A1C1E20]
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#_ REGISTER_IN v4 [01030507, 090B0D0F, 11131517, 191B1D1F]
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vavgsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [02040608, 0A0C0E10, 12141618, 1A1C1E20]
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#_ REGISTER_OUT v4 [01030507, 090B0D0F, 11131517, 191B1D1F]
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#_ REGISTER_OUT v5 [02040608, 0A0C0E10, 12141618, 1A1C1E20]
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test_vavgsb_2:
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#_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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#_ REGISTER_IN v4 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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vavgsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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#_ REGISTER_OUT v4 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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#_ REGISTER_OUT v5 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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test_vavgsb_3:
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#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
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vavgsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
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test_vavgsb_4:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vavgsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vavgsb_5:
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#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavgsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
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@ -1,9 +1,44 @@
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#vavgsh isn't implemented
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#test_vavgsh_1:
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# #_ REGISTER_IN v3 [00000001, 00020003, 00040005, 00060007]
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# #_ REGISTER_IN v4 [00080009, 000A000B, 000C000D, 000E000F]
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# vavgsh v5, v3, v4
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# blr
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# #_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
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# #_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
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# #_ REGISTER_OUT v5 [00040005, 00060007, 00080009, 000A000B]
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test_vavgsh_1:
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#_ REGISTER_IN v3 [00020004, 00060008, 000A000C, 000E0010]
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#_ REGISTER_IN v4 [00010003, 00050007, 0009000B, 000D000F]
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vavgsh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00020004, 00060008, 000A000C, 000E0010]
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#_ REGISTER_OUT v4 [00010003, 00050007, 0009000B, 000D000F]
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#_ REGISTER_OUT v5 [00020004, 00060008, 000A000C, 000E0010]
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test_vavgsh_2:
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#_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
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#_ REGISTER_IN v4 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
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vavgsh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
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#_ REGISTER_OUT v4 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
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#_ REGISTER_OUT v5 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
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test_vavgsh_3:
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#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_IN v4 [80008000, 80008000, 80008000, 80008000]
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vavgsh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_OUT v4 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_OUT v5 [80008000, 80008000, 80008000, 80008000]
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test_vavgsh_4:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vavgsh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vavgsh_5:
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#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavgsh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
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44
src/xenia/cpu/ppc/testing/instr_vavgsw.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vavgsw.s
Normal file
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@ -0,0 +1,44 @@
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test_vavgsw_1:
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#_ REGISTER_IN v3 [00000002, 00000004, 00000006, 00000008]
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#_ REGISTER_IN v4 [00000001, 00000003, 00000005, 00000007]
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vavgsw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000002, 00000004, 00000006, 00000008]
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#_ REGISTER_OUT v4 [00000001, 00000003, 00000005, 00000007]
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#_ REGISTER_OUT v5 [00000002, 00000004, 00000006, 00000008]
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test_vavgsw_2:
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#_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
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#_ REGISTER_IN v4 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
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vavgsw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
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#_ REGISTER_OUT v4 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
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#_ REGISTER_OUT v5 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
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test_vavgsw_3:
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#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_IN v4 [80000000, 80000000, 80000000, 80000000]
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vavgsw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_OUT v4 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
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test_vavgsw_4:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vavgsw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vavgsw_5:
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#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavgsw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
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44
src/xenia/cpu/ppc/testing/instr_vavgub.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vavgub.s
Normal file
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@ -0,0 +1,44 @@
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test_vavgub_1:
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#_ REGISTER_IN v3 [02040608, 0A0C0E10, 12141618, 1A1C1E20]
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#_ REGISTER_IN v4 [01030507, 090B0D0F, 11131517, 191B1D1F]
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vavgub v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [02040608, 0A0C0E10, 12141618, 1A1C1E20]
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#_ REGISTER_OUT v4 [01030507, 090B0D0F, 11131517, 191B1D1F]
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#_ REGISTER_OUT v5 [02040608, 0A0C0E10, 12141618, 1A1C1E20]
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test_vavgub_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vavgub v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vavgub_3:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavgub v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vavgub_4:
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#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
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vavgub v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
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test_vavgub_5:
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#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavgub v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
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@ -6,3 +6,39 @@ test_vavguh_1:
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#_ REGISTER_OUT v3 [00000001, 00020003, 00040005, 00060007]
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#_ REGISTER_OUT v4 [00080009, 000A000B, 000C000D, 000E000F]
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#_ REGISTER_OUT v5 [00040005, 00060007, 00080009, 000A000B]
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test_vavguh_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vavguh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vavguh_3:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavguh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vavguh_4:
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#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_IN v4 [80008000, 80008000, 80008000, 80008000]
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vavguh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_OUT v4 [80008000, 80008000, 80008000, 80008000]
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#_ REGISTER_OUT v5 [80008000, 80008000, 80008000, 80008000]
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test_vavguh_5:
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#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavguh v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
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44
src/xenia/cpu/ppc/testing/instr_vavguw.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vavguw.s
Normal file
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@ -0,0 +1,44 @@
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test_vavguw_1:
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#_ REGISTER_IN v3 [00000002, 00000004, 00000006, 00000008]
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#_ REGISTER_IN v4 [00000001, 00000003, 00000005, 00000007]
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vavguw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000002, 00000004, 00000006, 00000008]
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#_ REGISTER_OUT v4 [00000001, 00000003, 00000005, 00000007]
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#_ REGISTER_OUT v5 [00000002, 00000004, 00000006, 00000008]
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test_vavguw_2:
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#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vavguw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vavguw_3:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavguw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vavguw_4:
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#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_IN v4 [80000000, 80000000, 80000000, 80000000]
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vavguw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_OUT v4 [80000000, 80000000, 80000000, 80000000]
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#_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
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test_vavguw_5:
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#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_IN v4 [00000000, 00000000, 00000000, 00000000]
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vavguw v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
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#_ REGISTER_OUT v4 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
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44
src/xenia/cpu/ppc/testing/instr_vmaxsb.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vmaxsb.s
Normal file
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@ -0,0 +1,44 @@
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test_vmaxsb_1:
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#_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
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#_ REGISTER_IN v4 [10090807, 06050403, 02010011, 12131415]
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vmaxsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
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#_ REGISTER_OUT v4 [10090807, 06050403, 02010011, 12131415]
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#_ REGISTER_OUT v5 [10090807, 06060708, 090A0B11, 12131415]
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test_vmaxsb_2:
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#_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
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vmaxsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
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#_ REGISTER_OUT v5 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
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test_vmaxsb_3:
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#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vmaxsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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test_vmaxsb_4:
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#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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vmaxsb v5, v3, v4
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blr
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#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
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#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
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#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
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test_vmaxsb_5:
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#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vmaxsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
|
||||
|
|
@ -15,3 +15,39 @@ test_vmaxsh_2:
|
|||
#_ REGISTER_OUT v3 [00000009, 0002000B, 0004000D, 0006000F]
|
||||
#_ REGISTER_OUT v4 [00080001, 000A0003, 000C0005, 000E0007]
|
||||
#_ REGISTER_OUT v5 [00080009, 000A000B, 000C000D, 000E000F]
|
||||
|
||||
test_vmaxsh_3:
|
||||
#_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vmaxsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
|
||||
test_vmaxsh_4:
|
||||
#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vmaxsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vmaxsh_5:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vmaxsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vmaxsh_6:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vmaxsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
|
||||
|
|
|
|||
44
src/xenia/cpu/ppc/testing/instr_vmaxsw.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vmaxsw.s
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
test_vmaxsw_1:
|
||||
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_IN v4 [00000004, 00000003, 00000002, 00000001]
|
||||
vmaxsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_OUT v4 [00000004, 00000003, 00000002, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000004, 00000003, 00000003, 00000004]
|
||||
|
||||
test_vmaxsw_2:
|
||||
#_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vmaxsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
|
||||
test_vmaxsw_3:
|
||||
#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vmaxsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vmaxsw_4:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vmaxsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vmaxsw_5:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vmaxsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
|
||||
35
src/xenia/cpu/ppc/testing/instr_vmaxub.s
Normal file
35
src/xenia/cpu/ppc/testing/instr_vmaxub.s
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
test_vmaxub_1:
|
||||
#_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
|
||||
#_ REGISTER_IN v4 [10090807, 06050403, 02010011, 12131415]
|
||||
vmaxub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
|
||||
#_ REGISTER_OUT v4 [10090807, 06050403, 02010011, 12131415]
|
||||
#_ REGISTER_OUT v5 [10090807, 06060708, 090A0B11, 12131415]
|
||||
|
||||
test_vmaxub_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vmaxub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vmaxub_3:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
|
||||
vmaxub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
|
||||
|
||||
test_vmaxub_4:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vmaxub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
|
||||
|
|
@ -15,3 +15,30 @@ test_vmaxuh_2:
|
|||
#_ REGISTER_OUT v3 [00000009, 0002000B, 0004000D, 0006000F]
|
||||
#_ REGISTER_OUT v4 [00080001, 000A0003, 000C0005, 000E0007]
|
||||
#_ REGISTER_OUT v5 [00080009, 000A000B, 000C000D, 000E000F]
|
||||
|
||||
test_vmaxuh_3:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vmaxuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vmaxuh_4:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [80008000, 80008000, 80008000, 80008000]
|
||||
vmaxuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_OUT v5 [80008000, 80008000, 80008000, 80008000]
|
||||
|
||||
test_vmaxuh_5:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vmaxuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
|
||||
|
|
|
|||
35
src/xenia/cpu/ppc/testing/instr_vmaxuw.s
Normal file
35
src/xenia/cpu/ppc/testing/instr_vmaxuw.s
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
test_vmaxuw_1:
|
||||
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_IN v4 [00000004, 00000003, 00000002, 00000001]
|
||||
vmaxuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_OUT v4 [00000004, 00000003, 00000002, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000004, 00000003, 00000003, 00000004]
|
||||
|
||||
test_vmaxuw_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vmaxuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vmaxuw_3:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [80000000, 80000000, 80000000, 80000000]
|
||||
vmaxuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
|
||||
|
||||
test_vmaxuw_4:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vmaxuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
|
||||
44
src/xenia/cpu/ppc/testing/instr_vminsb.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vminsb.s
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
test_vminsb_1:
|
||||
#_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
|
||||
#_ REGISTER_IN v4 [10090807, 06050403, 02010011, 12131415]
|
||||
vminsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
|
||||
#_ REGISTER_OUT v4 [10090807, 06050403, 02010011, 12131415]
|
||||
#_ REGISTER_OUT v5 [01020304, 05050403, 0201000C, 0D0E0F10]
|
||||
|
||||
test_vminsb_2:
|
||||
#_ REGISTER_IN v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vminsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7F7F7F7F, 7F7F7F7F, 7F7F7F7F, 7F7F7F7F]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
|
||||
|
||||
test_vminsb_3:
|
||||
#_ REGISTER_IN v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vminsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [80808080, 80808080, 80808080, 80808080]
|
||||
|
||||
test_vminsb_4:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vminsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vminsb_5:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vminsb v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
|
||||
|
|
@ -15,3 +15,39 @@ test_vminsh_2:
|
|||
#_ REGISTER_OUT v3 [00000009, 0002000B, 0004000D, 0006000F]
|
||||
#_ REGISTER_OUT v4 [00080001, 000A0003, 000C0005, 000E0007]
|
||||
#_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
|
||||
|
||||
test_vminsh_3:
|
||||
#_ REGISTER_IN v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vminsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7FFF7FFF, 7FFF7FFF, 7FFF7FFF, 7FFF7FFF]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
|
||||
|
||||
test_vminsh_4:
|
||||
#_ REGISTER_IN v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vminsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [80008000, 80008000, 80008000, 80008000]
|
||||
|
||||
test_vminsh_5:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vminsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vminsh_6:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vminsh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
|
||||
|
|
|
|||
44
src/xenia/cpu/ppc/testing/instr_vminsw.s
Normal file
44
src/xenia/cpu/ppc/testing/instr_vminsw.s
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
test_vminsw_1:
|
||||
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_IN v4 [00000004, 00000003, 00000002, 00000001]
|
||||
vminsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_OUT v4 [00000004, 00000003, 00000002, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000002, 00000002, 00000001]
|
||||
|
||||
test_vminsw_2:
|
||||
#_ REGISTER_IN v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vminsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [7FFFFFFF, 7FFFFFFF, 7FFFFFFF, 7FFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
|
||||
|
||||
test_vminsw_3:
|
||||
#_ REGISTER_IN v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vminsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [80000000, 80000000, 80000000, 80000000]
|
||||
|
||||
test_vminsw_4:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
vminsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
|
||||
test_vminsw_5:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vminsw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
|
||||
35
src/xenia/cpu/ppc/testing/instr_vminub.s
Normal file
35
src/xenia/cpu/ppc/testing/instr_vminub.s
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
test_vminub_1:
|
||||
#_ REGISTER_IN v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
|
||||
#_ REGISTER_IN v4 [10090807, 06050403, 02010011, 12131415]
|
||||
vminub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01020304, 05060708, 090A0B0C, 0D0E0F10]
|
||||
#_ REGISTER_OUT v4 [10090807, 06050403, 02010011, 12131415]
|
||||
#_ REGISTER_OUT v5 [01020304, 05050403, 0201000C, 0D0E0F10]
|
||||
|
||||
test_vminub_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vminub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
|
||||
|
||||
test_vminub_3:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [80808080, 80808080, 80808080, 80808080]
|
||||
vminub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [80808080, 80808080, 80808080, 80808080]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vminub_4:
|
||||
#_ REGISTER_IN v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_IN v4 [01010101, 01010101, 01010101, 01010101]
|
||||
vminub v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v4 [01010101, 01010101, 01010101, 01010101]
|
||||
#_ REGISTER_OUT v5 [01010101, 01010101, 01010101, 01010101]
|
||||
|
|
@ -15,3 +15,30 @@ test_vminuh_2:
|
|||
#_ REGISTER_OUT v3 [00000009, 0002000B, 0004000D, 0006000F]
|
||||
#_ REGISTER_OUT v4 [00080001, 000A0003, 000C0005, 000E0007]
|
||||
#_ REGISTER_OUT v5 [00000001, 00020003, 00040005, 00060007]
|
||||
|
||||
test_vminuh_3:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vminuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
|
||||
|
||||
test_vminuh_4:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [80008000, 80008000, 80008000, 80008000]
|
||||
vminuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [80008000, 80008000, 80008000, 80008000]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vminuh_5:
|
||||
#_ REGISTER_IN v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_IN v4 [00010001, 00010001, 00010001, 00010001]
|
||||
vminuh v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v4 [00010001, 00010001, 00010001, 00010001]
|
||||
#_ REGISTER_OUT v5 [00010001, 00010001, 00010001, 00010001]
|
||||
|
|
|
|||
35
src/xenia/cpu/ppc/testing/instr_vminuw.s
Normal file
35
src/xenia/cpu/ppc/testing/instr_vminuw.s
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
test_vminuw_1:
|
||||
#_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_IN v4 [00000004, 00000003, 00000002, 00000001]
|
||||
vminuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
|
||||
#_ REGISTER_OUT v4 [00000004, 00000003, 00000002, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000002, 00000002, 00000001]
|
||||
|
||||
test_vminuw_2:
|
||||
#_ REGISTER_IN v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vminuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
|
||||
|
||||
test_vminuw_3:
|
||||
#_ REGISTER_IN v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_IN v4 [80000000, 80000000, 80000000, 80000000]
|
||||
vminuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
|
||||
#_ REGISTER_OUT v4 [80000000, 80000000, 80000000, 80000000]
|
||||
#_ REGISTER_OUT v5 [00000000, 00000000, 00000000, 00000000]
|
||||
|
||||
test_vminuw_4:
|
||||
#_ REGISTER_IN v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_IN v4 [00000001, 00000001, 00000001, 00000001]
|
||||
vminuw v5, v3, v4
|
||||
blr
|
||||
#_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v4 [00000001, 00000001, 00000001, 00000001]
|
||||
#_ REGISTER_OUT v5 [00000001, 00000001, 00000001, 00000001]
|
||||
Loading…
Add table
Add a link
Reference in a new issue