mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2025-12-06 03:31:59 +01:00
22e4df1577
- Not reset sweep on request - Better menu response - little DSP optimization Faster i2c bus (now 600kHz, allow more faster add settings) Add i2c command (disabled by default) Little fix stat command
229 lines
8.2 KiB
C
229 lines
8.2 KiB
C
/*
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* Copyright (c) 2014-2015, TAKAHASHI Tomohiro (TTRFTECH) edy555@gmail.com
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* All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* The software is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with GNU Radio; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "hal.h"
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#include "nanovna.h"
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#define REFCLK_8000KHZ
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#define AIC3204_ADDR 0x18
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#define wait_ms(ms) chThdSleepMilliseconds(ms)
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// Register - 0x01 / 0x34 (P1_R52): Left MICPGA Positive Terminal Input Routing Configuration
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#define REG_34_IN1L_TO_LEFT_P_NO (0<<6)
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#define REG_34_IN1L_TO_LEFT_P_10k (1<<6)
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#define REG_34_IN1L_TO_LEFT_P_20k (2<<6)
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#define REG_34_IN1L_TO_LEFT_P_40k (3<<6)
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#define REG_34_IN2L_TO_LEFT_P_NO (0<<4)
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#define REG_34_IN2L_TO_LEFT_P_10k (1<<4)
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#define REG_34_IN2L_TO_LEFT_P_20k (2<<4)
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#define REG_34_IN2L_TO_LEFT_P_40k (3<<4)
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#define REG_34_IN3L_TO_LEFT_P_NO (0<<2)
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#define REG_34_IN3L_TO_LEFT_P_10k (1<<2)
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#define REG_34_IN3L_TO_LEFT_P_20k (2<<2)
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#define REG_34_IN3L_TO_LEFT_P_40k (3<<2)
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#define REG_34_IN1R_TO_LEFT_P_NO (0<<0)
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#define REG_34_IN1R_TO_LEFT_P_10k (1<<0)
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#define REG_34_IN1R_TO_LEFT_P_20k (2<<0)
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#define REG_34_IN1R_TO_LEFT_P_40k (3<<0)
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// Register - 0x01 / 0x36 (P1_R54): Left MICPGA Negative Terminal Input Routing Configuration
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#define REG_36_CM1L_TO_LEFT_N_NO (0<<6)
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#define REG_36_CM1L_TO_LEFT_N_10k (1<<6)
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#define REG_36_CM1L_TO_LEFT_N_20k (2<<6)
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#define REG_36_CM1L_TO_LEFT_N_40k (3<<6)
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#define REG_36_IN2R_TO_LEFT_N_NO (0<<4)
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#define REG_36_IN2R_TO_LEFT_N_10k (1<<4)
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#define REG_36_IN2R_TO_LEFT_N_20k (2<<4)
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#define REG_36_IN2R_TO_LEFT_N_40k (3<<4)
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#define REG_36_IN3R_TO_LEFT_N_NO (0<<2)
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#define REG_36_IN3R_TO_LEFT_N_10k (1<<2)
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#define REG_36_IN3R_TO_LEFT_N_20k (2<<2)
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#define REG_36_IN3R_TO_LEFT_N_40k (3<<2)
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#define REG_36_CM2L_TO_LEFT_N_NO (0<<0)
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#define REG_36_CM2L_TO_LEFT_N_10k (1<<0)
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#define REG_36_CM2L_TO_LEFT_N_20k (2<<0)
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#define REG_36_CM2L_TO_LEFT_N_40k (3<<0)
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// Register - 0x01 / 0x37 (P1_R55): Right MICPGA Positive Terminal Input Routing Configuration
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#define REG_37_IN1R_TO_RIGHT_P_NO (0<<6)
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#define REG_37_IN1R_TO_RIGHT_P_10k (1<<6)
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#define REG_37_IN1R_TO_RIGHT_P_20k (2<<6)
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#define REG_37_IN1R_TO_RIGHT_P_40k (3<<6)
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#define REG_37_IN2R_TO_RIGHT_P_NO (0<<4)
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#define REG_37_IN2R_TO_RIGHT_P_10k (1<<4)
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#define REG_37_IN2R_TO_RIGHT_P_20k (2<<4)
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#define REG_37_IN2R_TO_RIGHT_P_40k (3<<4)
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#define REG_37_IN3R_TO_RIGHT_P_NO (0<<2)
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#define REG_37_IN3R_TO_RIGHT_P_10k (1<<2)
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#define REG_37_IN3R_TO_RIGHT_P_20k (2<<2)
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#define REG_37_IN3R_TO_RIGHT_P_40k (3<<2)
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#define REG_37_IN2L_TO_RIGHT_P_NO (0<<0)
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#define REG_37_IN2L_TO_RIGHT_P_10k (1<<0)
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#define REG_37_IN2L_TO_RIGHT_P_20k (2<<0)
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#define REG_37_IN2L_TO_RIGHT_P_40k (3<<0)
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// Register - 0x01 / 0x39 (P1_R57): Right MICPGA Negative Terminal Input Routing Configuration
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#define REG_39_CM1R_TO_RIGHT_N_NO (0<<6)
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#define REG_39_CM1R_TO_RIGHT_N_10k (1<<6)
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#define REG_39_CM1R_TO_RIGHT_N_20k (2<<6)
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#define REG_39_CM1R_TO_RIGHT_N_40k (3<<6)
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#define REG_39_IN1L_TO_RIGHT_N_NO (0<<4)
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#define REG_39_IN1L_TO_RIGHT_N_10k (1<<4)
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#define REG_39_IN1L_TO_RIGHT_N_20k (2<<4)
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#define REG_39_IN1L_TO_RIGHT_N_40k (3<<4)
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#define REG_39_IN3L_TO_RIGHT_N_NO (0<<2)
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#define REG_39_IN3L_TO_RIGHT_N_10k (1<<2)
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#define REG_39_IN3L_TO_RIGHT_N_20k (2<<2)
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#define REG_39_IN3L_TO_RIGHT_N_40k (3<<2)
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#define REG_39_CM2R_TO_RIGHT_N_NO (0<<0)
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#define REG_39_CM2R_TO_RIGHT_N_10k (1<<0)
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#define REG_39_CM2R_TO_RIGHT_N_20k (2<<0)
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#define REG_39_CM2R_TO_RIGHT_N_40k (3<<0)
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static const uint8_t conf_data[] = {
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// reg, data,
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// PLL clock config
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0x00, 0x00, /* Initialize to Page 0 */
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0x01, 0x01, /* Initialize the device through software reset */
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0x04, 0x43, /* PLL Clock High, MCLK, PLL */
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#ifdef REFCLK_8000KHZ
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/* 8.000MHz*10.7520 = 86.016MHz, 86.016MHz/(2*7*128) = 48kHz */
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0x05, 0x91, /* Power up PLL, P=1,R=1 */
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0x06, 0x0a, /* J=10 */
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0x07, 29, /* D=7520 = (29<<8) + 96 */
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0x08, 96,
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#endif
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// Clock config, default fs=48kHz
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0x0b, 0x82, /* Power up the NDAC divider with value 2 */
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0x0c, 0x87, /* Power up the MDAC divider with value 7 */
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0x0d, 0x00, /* Program the OSR of DAC to 128 */
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0x0e, 0x80,
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0x3c, 0x08, /* Set the DAC Mode to PRB_P8 */
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//0x3c, 25, /* Set the DAC Mode to PRB_P25 */
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0x1b, 0x0c, /* Set the BCLK,WCLK as output */
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0x1e, 0x80 + 28, /* Enable the BCLKN divider with value 28 */
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0x25, 0xee, /* DAC power up */
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0x12, 0x82, /* Power up the NADC divider with value 2 */
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0x13, 0x87, /* Power up the MADC divider with value 7 */
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0x14, 0x80, /* Program the OSR of ADC to 128 */
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0x3d, 0x01, /* Select ADC PRB_R1 */
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// Data routing
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0x00, 0x01, /* Select Page 1 */
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0x01, 0x08, /* Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO*/
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0x02, 0x01, /* Enable Master Analog Power Control */
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0x7b, 0x01, /* Set the REF charging time to 40ms */
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0x14, 0x25, /* HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. */
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0x0a, 0x33, /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */
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0x3d, 0x00, /* Select ADC PTM_R4 */
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0x47, 0x32, /* Set MicPGA startup delay to 6.4ms */
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0x7b, 0x01, /* Set the REF charging time to 40ms */
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0x34, REG_34_IN2L_TO_LEFT_P_10k, /* Route IN2L to LEFT_P with 10K */
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0x36, REG_36_IN2R_TO_LEFT_N_10k, /* Route IN2R to LEFT_N with 10K */
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//0x37, 0x04, /* Route IN3R to RIGHT_P with 10K */
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//0x39, 0x04, /* Route IN3L to RIGHT_N with 10K */
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//0x3b, 0x00, /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */
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//0x3c, 0x00, /* Unmute Right MICPGA, Gain selection of 32dB to make channel gain 0dB */
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};
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static const uint8_t conf_data_unmute[] = {
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// reg, data,
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0x00, 0x00, /* Select Page 0 */
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0x51, 0xc0, /* Power up Left and Right ADC Channels */
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0x52, 0x00, /* Unmute Left and Right ADC Digital Volume Control */
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};
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static const uint8_t conf_data_ch3_select[] = {
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// reg, data,
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0x00, 0x01, /* Select Page 1 */
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0x37, REG_37_IN3R_TO_RIGHT_P_10k, /* Route IN3R to RIGHT_P with input impedance of 10K */
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0x39, REG_39_IN3L_TO_RIGHT_N_10k, /* Route IN3L to RIGHT_N with input impedance of 10K */
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};
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static const uint8_t conf_data_ch1_select[] = {
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// reg, data,
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0x00, 0x01, /* Select Page 1 */
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0x37, REG_37_IN1R_TO_RIGHT_P_10k, /* Route IN1R to RIGHT_P with input impedance of 10K */
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0x39, REG_39_IN1L_TO_RIGHT_N_10k, /* Route IN1L to RIGHT_N with input impedance of 10K */
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};
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static inline void
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tlv320aic3204_bulk_write(const uint8_t *buf, int len)
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{
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(void)i2cMasterTransmitTimeout(&I2CD1, AIC3204_ADDR, buf, len, NULL, 0, 1000);
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}
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#if 0
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static int
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tlv320aic3204_read(uint8_t d0)
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{
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int addr = AIC3204_ADDR;
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uint8_t buf[] = { d0 };
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i2cAcquireBus(&I2CD1);
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i2cMasterTransmitTimeout(&I2CD1, addr, buf, 1, buf, 1, 1000);
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i2cReleaseBus(&I2CD1);
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return buf[0];
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}
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#endif
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static void
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tlv320aic3204_config(const uint8_t *data, int len)
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{
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i2cAcquireBus(&I2CD1);
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for (; len--; data += 2)
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tlv320aic3204_bulk_write(data, 2);
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i2cReleaseBus(&I2CD1);
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}
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void tlv320aic3204_init(void)
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{
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tlv320aic3204_config(conf_data, sizeof(conf_data)/2);
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wait_ms(40);
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tlv320aic3204_config(conf_data_unmute, sizeof(conf_data_unmute)/2);
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}
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void tlv320aic3204_select(int channel)
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{
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tlv320aic3204_config(channel ? conf_data_ch1_select : conf_data_ch3_select, sizeof(conf_data_ch3_select)/2);
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}
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void tlv320aic3204_set_gain(int lgain, int rgain)
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{
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uint8_t data[] = {
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0x00, 0x01, /* Select Page 1 */
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0x3b, lgain, /* Unmute Left MICPGA, set gain */
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0x3c, rgain, /* Unmute Right MICPGA, set gain */
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};
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tlv320aic3204_config(data, sizeof(data)/2);
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}
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