mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2026-01-10 18:40:10 +01:00
Little rework bandwidth:
- Not reset sweep on request - Better menu response - little DSP optimization Faster i2c bus (now 600kHz, allow more faster add settings) Add i2c command (disabled by default) Little fix stat command
This commit is contained in:
DiSlord
parent
5a10105b1a
commit
22e4df1577
32
dsp.c
32
dsp.c
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@ -40,11 +40,27 @@ const int16_t sincos_tbl[48][2] = {
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{ 32138, 6393 }, { 29389, -14493 }, { 14493, -29389 }, { -6393, -32138 },
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{-24636, -21605 }, {-32698, -2143 }, {-27246, 18205 }, {-10533, 31029 }
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};
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#if 0
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void generate_DSP_Table(int offset){
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float audio_freq = 48000.0;
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// N = offset * AUDIO_SAMPLES_COUNT / audio_freq; should be integer
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// AUDIO_SAMPLES_COUNT = N * audio_freq / offset; N - minimum integer value for get integer SAMPLE_LEN
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// Bandwidth on one step = audio_freq / AUDIO_SAMPLES_COUNT
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float step = 2 * VNA_PI * offset / audio_freq;
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float v = step/2;
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for (int i=0; i<AUDIO_SAMPLES_COUNT; i++){
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sincos_tbl[i][0] = sin(v)*32768.0 + 0.5;
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sincos_tbl[i][1] = cos(v)*32768.0 + 0.5;
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v+=step;
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}
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}
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#endif
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float acc_samp_s;
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float acc_samp_c;
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float acc_ref_s;
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float acc_ref_c;
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typedef float acc_t;
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acc_t acc_samp_s;
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acc_t acc_samp_c;
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acc_t acc_ref_s;
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acc_t acc_ref_c;
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void
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dsp_process(int16_t *capture, size_t length)
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@ -67,10 +83,10 @@ dsp_process(int16_t *capture, size_t length)
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#endif
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int32_t s = sincos_tbl[i][0];
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int32_t c = sincos_tbl[i][1];
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samp_s += smp * s / 16;
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samp_c += smp * c / 16;
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ref_s += ref * s / 16;
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ref_c += ref * c / 16;
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samp_s += (smp * s)>>4;
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samp_c += (smp * c)>>4;
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ref_s += (ref * s)>>4;
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ref_c += (ref * c)>>4;
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#if 0
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uint32_t sc = *(uint32_t)&sincos_tbl[i];
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samp_s = __SMLABB(sr, sc, samp_s);
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309
main.c
309
main.c
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@ -70,6 +70,8 @@ static volatile vna_shellcmd_t shell_function = 0;
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// Enable color command, allow change config color for traces, grid, menu
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#define ENABLE_COLOR_COMMAND
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//#define ENABLE_I2C_COMMAND
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static void apply_error_term_at(int i);
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static void apply_edelay_at(int i);
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static void cal_interpolate(int s);
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@ -88,6 +90,16 @@ static int8_t drive_strength = DRIVE_STRENGTH_AUTO;
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int8_t sweep_mode = SWEEP_ENABLE;
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volatile uint8_t redraw_request = 0; // contains REDRAW_XXX flags
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// sweep operation variables
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volatile uint8_t wait_count = 0;
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static uint8_t accumerate_count = 0;
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static uint16_t p_sweep = 0;
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// ChibiOS i2s buffer must be 2x size (for process one while next buffer filled by DMA)
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static int16_t rx_buffer[AUDIO_BUFFER_LEN * 2];
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// Sweep measured data
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float measured[2][POINTS_COUNT][2];
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// Version text, displayed in Config->Version menu, also send by info command
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const char *info_about[]={
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BOARD_NAME,
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@ -474,7 +486,9 @@ VNA_SHELL_FUNCTION(cmd_offset)
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shell_printf("usage: offset {frequency offset(Hz)}\r\n");
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return;
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}
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si5351_set_frequency_offset(my_atoi(argv[0]));
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int32_t offset = my_atoi(argv[0]);
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// generate_DSP_Table(offset);
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si5351_set_frequency_offset(offset);
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}
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VNA_SHELL_FUNCTION(cmd_freq)
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@ -577,94 +591,6 @@ static struct {
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#endif
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} stat;
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int16_t rx_buffer[AUDIO_BUFFER_LEN * 2];
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#ifdef ENABLED_DUMP
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int16_t dump_buffer[AUDIO_BUFFER_LEN];
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int16_t dump_selection = 0;
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#endif
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volatile uint8_t wait_count = 0;
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volatile uint8_t accumerate_count = 0;
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const int8_t bandwidth_accumerate_count[] = {
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1, // 1kHz
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3, // 300Hz
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10, // 100Hz
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33, // 30Hz
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100 // 10Hz
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};
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float measured[2][POINTS_COUNT][2];
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static inline void
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dsp_start(int count)
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{
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wait_count = count;
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accumerate_count = bandwidth_accumerate_count[bandwidth];
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reset_dsp_accumerator();
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}
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static inline void
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dsp_wait(void)
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{
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while (accumerate_count > 0)
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__WFI();
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}
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#ifdef ENABLED_DUMP
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static void
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duplicate_buffer_to_dump(int16_t *p)
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{
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if (dump_selection == 1)
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p = samp_buf;
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else if (dump_selection == 2)
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p = ref_buf;
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memcpy(dump_buffer, p, sizeof dump_buffer);
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}
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#endif
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void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n)
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{
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#if PORT_SUPPORTS_RT
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int32_t cnt_s = port_rt_get_counter_value();
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int32_t cnt_e;
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#endif
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int16_t *p = &rx_buffer[offset];
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(void)i2sp;
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(void)n;
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if (wait_count > 1) {
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--wait_count;
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} else if (wait_count > 0) {
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if (accumerate_count > 0) {
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dsp_process(p, n);
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accumerate_count--;
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}
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#ifdef ENABLED_DUMP
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duplicate_buffer_to_dump(p);
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#endif
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}
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#if PORT_SUPPORTS_RT
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cnt_e = port_rt_get_counter_value();
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stat.interval_cycles = cnt_s - stat.last_counter_value;
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stat.busy_cycles = cnt_e - cnt_s;
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stat.last_counter_value = cnt_s;
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#endif
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stat.callback_count++;
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}
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static const I2SConfig i2sconfig = {
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NULL, // TX Buffer
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rx_buffer, // RX Buffer
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AUDIO_BUFFER_LEN * 2,
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NULL, // tx callback
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i2s_end_callback, // rx callback
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0, // i2scfgr
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2 // i2spr
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};
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VNA_SHELL_FUNCTION(cmd_data)
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{
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int i;
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@ -819,6 +745,7 @@ void load_default_properties(void)
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current_props._active_marker = 0;
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current_props._domain_mode = 0;
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current_props._marker_smith_format = MS_RLC;
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current_props._bandwidth = 0;
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//Checksum add on caldata_save
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//current_props.checksum = 0;
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}
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@ -835,45 +762,116 @@ ensure_edit_config(void)
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cal_status = 0;
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}
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#ifdef ENABLED_DUMP
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int16_t dump_buffer[AUDIO_BUFFER_LEN];
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int16_t dump_selection = 0;
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#endif
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#ifdef ENABLED_DUMP
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static void
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duplicate_buffer_to_dump(int16_t *p)
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{
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if (dump_selection == 1)
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p = samp_buf;
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else if (dump_selection == 2)
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p = ref_buf;
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memcpy(dump_buffer, p, sizeof dump_buffer);
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}
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#endif
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//
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// DMA i2s callback function, called on get 'half' and 'full' buffer size data
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// need for process data, while DMA fill next buffer
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void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n)
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{
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#if PORT_SUPPORTS_RT
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int32_t cnt_s = port_rt_get_counter_value();
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int32_t cnt_e;
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#endif
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int16_t *p = &rx_buffer[offset];
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(void)i2sp;
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if (wait_count > 0){
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if (wait_count <= accumerate_count){
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if (wait_count == accumerate_count)
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reset_dsp_accumerator();
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dsp_process(p, n);
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}
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#ifdef ENABLED_DUMP
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duplicate_buffer_to_dump(p);
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#endif
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--wait_count;
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}
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#if PORT_SUPPORTS_RT
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cnt_e = port_rt_get_counter_value();
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stat.interval_cycles = cnt_s - stat.last_counter_value;
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stat.busy_cycles = cnt_e - cnt_s;
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stat.last_counter_value = cnt_s;
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#endif
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stat.callback_count++;
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}
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// Bandwidth depend from AUDIO_SAMPLES_COUNT and audio ADC frequency
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// for AUDIO_SAMPLES_COUNT = 48 and ADC = 48kHz one measure give 48000/48=1000Hz
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static const int8_t bandwidth_accumerate_count[] = {
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1, // 1kHz
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3, // 300Hz
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10, // 100Hz
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33, // 30Hz
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100 // 10Hz
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};
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static const I2SConfig i2sconfig = {
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NULL, // TX Buffer
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rx_buffer, // RX Buffer
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sizeof(rx_buffer), // RX Buffer size
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NULL, // tx callback
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i2s_end_callback, // rx callback
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0, // i2scfgr
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0 // i2spr
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};
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#define DSP_START(delay) {accumerate_count = bandwidth_accumerate_count[bandwidth]; wait_count = delay-1 + accumerate_count;}
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#define DSP_WAIT_READY while (wait_count) {if (operation_requested && break_on_operation) return false; __WFI();}
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#define DSP_WAIT while (wait_count) {__WFI();}
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#define RESET_SWEEP {p_sweep = 0;}
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#define DELAY_CHANNEL_CHANGE 2
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// main loop for measurement
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bool sweep(bool break_on_operation)
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{
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int i, delay;
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int delay=1;
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if (p_sweep>=sweep_points || break_on_operation == false) RESET_SWEEP;
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// blink LED while scanning
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palClearPad(GPIOC, GPIOC_LED);
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// Power stabilization after LED off, also align timings on i == 0
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for (i = 0; i < sweep_points; i++) { // 5300
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if (frequencies[i] == 0) break;
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delay = set_frequency(frequencies[i]); // 700
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for (; p_sweep < sweep_points; p_sweep++) { // 5300
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if (frequencies[p_sweep] == 0) break;
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delay+= set_frequency(frequencies[p_sweep]);
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tlv320aic3204_select(0); // 60 CH0:REFLECT, reset and begin measure
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dsp_start(delay + ((i == 0) ? 1 : 0)); // 1900
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DSP_START(delay);
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delay = 0;
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//================================================
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// Place some code thats need execute while delay
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//================================================
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dsp_wait();
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// calculate reflection coefficient
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(*sample_func)(measured[0][i]); // 60
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DSP_WAIT_READY;
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(*sample_func)(measured[0][p_sweep]); // calculate reflection coefficient
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tlv320aic3204_select(1); // 60 CH1:TRANSMISSION, reset and begin measure
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dsp_start(DELAY_CHANNEL_CHANGE); // 1700
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DSP_START(DELAY_CHANNEL_CHANGE);
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//================================================
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// Place some code thats need execute while delay
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//================================================
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dsp_wait();
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// calculate transmission coefficient
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(*sample_func)(measured[1][i]); // 60
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DSP_WAIT_READY;
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(*sample_func)(measured[1][p_sweep]); // calculate transmission coefficient
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// ======== 170 ===========
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if (cal_status & CALSTAT_APPLY)
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apply_error_term_at(i);
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apply_error_term_at(p_sweep);
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if (electrical_delay != 0)
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apply_edelay_at(i);
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// back to toplevel to handle ui operation
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if (operation_requested && break_on_operation)
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return false;
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apply_edelay_at(p_sweep);
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// Display SPI made noise on measurement (can see in CW mode)
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// ili9341_fill(OFFSETX+CELLOFFSETX, OFFSETY, (p_sweep * WIDTH)/(sweep_points-1), 1, RGB565(0,0,255));
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}
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// blink LED while scanning
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palSetPad(GPIOC, GPIOC_LED);
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@ -987,6 +985,7 @@ update_frequencies(void)
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// set grid layout
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update_grid();
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RESET_SWEEP;
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}
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void
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@ -1537,7 +1536,7 @@ static const struct {
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const char *name;
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uint16_t refpos;
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float scale_unit;
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} trace_info[] = {
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} trace_info[MAX_TRACE_TYPE-1] = {
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{ "LOGMAG", NGRIDY-1, 10.0 },
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{ "PHASE", NGRIDY/2, 90.0 },
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{ "DELAY", NGRIDY/2, 1e-9 },
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@ -1950,30 +1949,49 @@ VNA_SHELL_FUNCTION(cmd_stat)
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int16_t *p = &rx_buffer[0];
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int32_t acc0, acc1;
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int32_t ave0, ave1;
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// float sample[2], ref[2];
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// minr, maxr, mins, maxs;
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int32_t count = AUDIO_BUFFER_LEN;
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int i;
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(void)argc;
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(void)argv;
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acc0 = acc1 = 0;
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for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) {
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acc0 += p[i];
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acc1 += p[i+1];
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}
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ave0 = acc0 / count;
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ave1 = acc1 / count;
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acc0 = acc1 = 0;
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for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) {
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acc0 += (p[i] - ave0)*(p[i] - ave0);
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acc1 += (p[i+1] - ave1)*(p[i+1] - ave1);
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}
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stat.rms[0] = sqrtf(acc0 / count);
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stat.rms[1] = sqrtf(acc1 / count);
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stat.ave[0] = ave0;
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stat.ave[1] = ave1;
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for (int ch=0;ch<2;ch++){
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tlv320aic3204_select(ch);
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DSP_START(4);
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DSP_WAIT;
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// reset_dsp_accumerator();
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// dsp_process(&p[ 0], AUDIO_BUFFER_LEN);
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// dsp_process(&p[AUDIO_BUFFER_LEN], AUDIO_BUFFER_LEN);
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shell_printf("average: %d %d\r\n", stat.ave[0], stat.ave[1]);
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shell_printf("rms: %d %d\r\n", stat.rms[0], stat.rms[1]);
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shell_printf("callback count: %d\r\n", stat.callback_count);
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acc0 = acc1 = 0;
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for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) {
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acc0 += p[i ];
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acc1 += p[i+1];
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}
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ave0 = acc0 / count;
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ave1 = acc1 / count;
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acc0 = acc1 = 0;
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// minr = maxr = 0;
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// mins = maxs = 0;
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for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) {
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acc0 += (p[i ] - ave0)*(p[i ] - ave0);
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acc1 += (p[i+1] - ave1)*(p[i+1] - ave1);
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// if (minr < p[i ]) minr = p[i ];
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// if (maxr > p[i ]) maxr = p[i ];
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// if (mins < p[i+1]) mins = p[i+1];
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// if (maxs > p[i+1]) maxs = p[i+1];
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}
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stat.rms[0] = sqrtf(acc0 / count);
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stat.rms[1] = sqrtf(acc1 / count);
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stat.ave[0] = ave0;
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stat.ave[1] = ave1;
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shell_printf("Ch: %d\r\n", ch);
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shell_printf("average: r: %6d s: %6d\r\n", stat.ave[0], stat.ave[1]);
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shell_printf("rms: r: %6d s: %6d\r\n", stat.rms[0], stat.rms[1]);
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// shell_printf("min: ref %6d ch %6d\r\n", minr, mins);
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// shell_printf("max: ref %6d ch %6d\r\n", maxr, maxs);
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}
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//shell_printf("callback count: %d\r\n", stat.callback_count);
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//shell_printf("interval cycle: %d\r\n", stat.interval_cycles);
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//shell_printf("busy cycle: %d\r\n", stat.busy_cycles);
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//shell_printf("load: %d\r\n", stat.busy_cycles * 100 / stat.interval_cycles);
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@ -2072,6 +2090,20 @@ VNA_SHELL_FUNCTION(cmd_color)
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}
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#endif
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#ifdef ENABLE_I2C_COMMAND
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VNA_SHELL_FUNCTION(cmd_i2c){
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uint8_t page = my_atoui(argv[0]);
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uint8_t reg = my_atoui(argv[1]);
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uint8_t data = my_atoui(argv[2]);
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uint8_t d1[] = {0x00, page};
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uint8_t d2[] = { reg, data};
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i2cAcquireBus(&I2CD1);
|
||||
(void)i2cMasterTransmitTimeout(&I2CD1, 0x18, d1, 2, NULL, 0, 1000);
|
||||
(void)i2cMasterTransmitTimeout(&I2CD1, 0x18, d2, 2, NULL, 0, 1000);
|
||||
i2cReleaseBus(&I2CD1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_THREADS_COMMAND
|
||||
#if CH_CFG_USE_REGISTRY == FALSE
|
||||
#error "Threads Requite enabled CH_CFG_USE_REGISTRY in chconf.h"
|
||||
|
|
@ -2121,7 +2153,7 @@ static const VNAShellCommand commands[] =
|
|||
{"version" , cmd_version , 0},
|
||||
{"reset" , cmd_reset , 0},
|
||||
{"freq" , cmd_freq , CMD_WAIT_MUTEX},
|
||||
{"offset" , cmd_offset , 0},
|
||||
{"offset" , cmd_offset , CMD_WAIT_MUTEX},
|
||||
#ifdef ENABLE_TIME_COMMAND
|
||||
{"time" , cmd_time , 0},
|
||||
#endif
|
||||
|
|
@ -2134,8 +2166,8 @@ static const VNAShellCommand commands[] =
|
|||
#endif
|
||||
{"frequencies" , cmd_frequencies , 0},
|
||||
{"port" , cmd_port , 0},
|
||||
{"stat" , cmd_stat , 0},
|
||||
{"gain" , cmd_gain , 0},
|
||||
{"stat" , cmd_stat , CMD_WAIT_MUTEX},
|
||||
{"gain" , cmd_gain , CMD_WAIT_MUTEX},
|
||||
{"power" , cmd_power , 0},
|
||||
{"sample" , cmd_sample , 0},
|
||||
// {"gamma" , cmd_gamma , 0},
|
||||
|
|
@ -2166,6 +2198,9 @@ static const VNAShellCommand commands[] =
|
|||
#ifdef ENABLE_COLOR_COMMAND
|
||||
{"color" , cmd_color , 0},
|
||||
#endif
|
||||
#ifdef ENABLE_I2C_COMMAND
|
||||
{"i2c" , cmd_i2c , CMD_WAIT_MUTEX},
|
||||
#endif
|
||||
#ifdef ENABLE_THREADS_COMMAND
|
||||
{"threads" , cmd_threads , 0},
|
||||
#endif
|
||||
|
|
@ -2307,13 +2342,13 @@ static const I2CConfig i2ccfg = {
|
|||
#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
|
||||
// STM32_I2C1SW == STM32_I2C1SW_SYSCLK (SYSCLK = 48MHz)
|
||||
// 400kHz @ SYSCLK 48MHz (Use 26.4.10 I2C_TIMINGR register configuration examples from STM32 RM0091 Reference manual)
|
||||
STM32_TIMINGR_PRESC(5U) |
|
||||
STM32_TIMINGR_SCLDEL(3U) | STM32_TIMINGR_SDADEL(3U) |
|
||||
STM32_TIMINGR_SCLH(3U) | STM32_TIMINGR_SCLL(9U),
|
||||
// STM32_TIMINGR_PRESC(5U) |
|
||||
// STM32_TIMINGR_SCLDEL(3U) | STM32_TIMINGR_SDADEL(3U) |
|
||||
// STM32_TIMINGR_SCLH(3U) | STM32_TIMINGR_SCLL(9U),
|
||||
// 600kHz @ SYSCLK 48MHz, manually get values, x1.5 I2C speed, but need calc timings
|
||||
// STM32_TIMINGR_PRESC(3U) |
|
||||
// STM32_TIMINGR_SCLDEL(2U) | STM32_TIMINGR_SDADEL(2U) |
|
||||
// STM32_TIMINGR_SCLH(4U) | STM32_TIMINGR_SCLL(4U),
|
||||
STM32_TIMINGR_PRESC(3U) |
|
||||
STM32_TIMINGR_SCLDEL(2U) | STM32_TIMINGR_SDADEL(2U) |
|
||||
STM32_TIMINGR_SCLH(4U) | STM32_TIMINGR_SCLL(4U),
|
||||
#else
|
||||
#error "Need Define STM32_I2C1SW and set correct TIMINGR settings"
|
||||
#endif
|
||||
|
|
@ -2336,7 +2371,7 @@ int main(void)
|
|||
{
|
||||
halInit();
|
||||
chSysInit();
|
||||
|
||||
// generate_DSP_Table(FREQUENCY_OFFSET);
|
||||
//palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN);
|
||||
//palSetPadMode(GPIOB, 9, PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN);
|
||||
i2cStart(&I2CD1, &i2ccfg);
|
||||
|
|
|
|||
10
nanovna.h
10
nanovna.h
|
|
@ -104,12 +104,9 @@ extern const char *info_about[];
|
|||
* dsp.c
|
||||
*/
|
||||
// 5ms @ 48kHz
|
||||
#define AUDIO_BUFFER_LEN 96
|
||||
|
||||
extern int16_t rx_buffer[];
|
||||
|
||||
#define STATE_LEN 32
|
||||
#define SAMPLE_LEN 48
|
||||
#define AUDIO_SAMPLES_COUNT 48
|
||||
// Buffer contain left and right channel samples (need x2)
|
||||
#define AUDIO_BUFFER_LEN (AUDIO_SAMPLES_COUNT*2)
|
||||
|
||||
#ifdef ENABLED_DUMP
|
||||
extern int16_t ref_buf[];
|
||||
|
|
@ -121,6 +118,7 @@ void reset_dsp_accumerator(void);
|
|||
void calculate_gamma(float *gamma);
|
||||
void fetch_amplitude(float *gamma);
|
||||
void fetch_amplitude_ref(float *gamma);
|
||||
void generate_DSP_Table(int offset);
|
||||
|
||||
/*
|
||||
* tlv320aic3204.c
|
||||
|
|
|
|||
2
si5351.c
2
si5351.c
|
|
@ -44,7 +44,7 @@ static int32_t current_offset = FREQUENCY_OFFSET;
|
|||
#define DELAY_NORMAL 2
|
||||
// Delay for bands (depend set band 1 more fast (can change before next dsp buffer ready, need wait additional interval)
|
||||
#define DELAY_BAND_1 3
|
||||
#define DELAY_BAND_2 2
|
||||
#define DELAY_BAND_2 3
|
||||
// Band changes need set delay after reset PLL
|
||||
#define DELAY_BANDCHANGE_1 3
|
||||
#define DELAY_BANDCHANGE_2 3
|
||||
|
|
|
|||
|
|
@ -25,6 +25,90 @@
|
|||
|
||||
#define wait_ms(ms) chThdSleepMilliseconds(ms)
|
||||
|
||||
// Register - 0x01 / 0x34 (P1_R52): Left MICPGA Positive Terminal Input Routing Configuration
|
||||
#define REG_34_IN1L_TO_LEFT_P_NO (0<<6)
|
||||
#define REG_34_IN1L_TO_LEFT_P_10k (1<<6)
|
||||
#define REG_34_IN1L_TO_LEFT_P_20k (2<<6)
|
||||
#define REG_34_IN1L_TO_LEFT_P_40k (3<<6)
|
||||
|
||||
#define REG_34_IN2L_TO_LEFT_P_NO (0<<4)
|
||||
#define REG_34_IN2L_TO_LEFT_P_10k (1<<4)
|
||||
#define REG_34_IN2L_TO_LEFT_P_20k (2<<4)
|
||||
#define REG_34_IN2L_TO_LEFT_P_40k (3<<4)
|
||||
|
||||
#define REG_34_IN3L_TO_LEFT_P_NO (0<<2)
|
||||
#define REG_34_IN3L_TO_LEFT_P_10k (1<<2)
|
||||
#define REG_34_IN3L_TO_LEFT_P_20k (2<<2)
|
||||
#define REG_34_IN3L_TO_LEFT_P_40k (3<<2)
|
||||
|
||||
#define REG_34_IN1R_TO_LEFT_P_NO (0<<0)
|
||||
#define REG_34_IN1R_TO_LEFT_P_10k (1<<0)
|
||||
#define REG_34_IN1R_TO_LEFT_P_20k (2<<0)
|
||||
#define REG_34_IN1R_TO_LEFT_P_40k (3<<0)
|
||||
|
||||
// Register - 0x01 / 0x36 (P1_R54): Left MICPGA Negative Terminal Input Routing Configuration
|
||||
#define REG_36_CM1L_TO_LEFT_N_NO (0<<6)
|
||||
#define REG_36_CM1L_TO_LEFT_N_10k (1<<6)
|
||||
#define REG_36_CM1L_TO_LEFT_N_20k (2<<6)
|
||||
#define REG_36_CM1L_TO_LEFT_N_40k (3<<6)
|
||||
|
||||
#define REG_36_IN2R_TO_LEFT_N_NO (0<<4)
|
||||
#define REG_36_IN2R_TO_LEFT_N_10k (1<<4)
|
||||
#define REG_36_IN2R_TO_LEFT_N_20k (2<<4)
|
||||
#define REG_36_IN2R_TO_LEFT_N_40k (3<<4)
|
||||
|
||||
#define REG_36_IN3R_TO_LEFT_N_NO (0<<2)
|
||||
#define REG_36_IN3R_TO_LEFT_N_10k (1<<2)
|
||||
#define REG_36_IN3R_TO_LEFT_N_20k (2<<2)
|
||||
#define REG_36_IN3R_TO_LEFT_N_40k (3<<2)
|
||||
|
||||
#define REG_36_CM2L_TO_LEFT_N_NO (0<<0)
|
||||
#define REG_36_CM2L_TO_LEFT_N_10k (1<<0)
|
||||
#define REG_36_CM2L_TO_LEFT_N_20k (2<<0)
|
||||
#define REG_36_CM2L_TO_LEFT_N_40k (3<<0)
|
||||
|
||||
// Register - 0x01 / 0x37 (P1_R55): Right MICPGA Positive Terminal Input Routing Configuration
|
||||
#define REG_37_IN1R_TO_RIGHT_P_NO (0<<6)
|
||||
#define REG_37_IN1R_TO_RIGHT_P_10k (1<<6)
|
||||
#define REG_37_IN1R_TO_RIGHT_P_20k (2<<6)
|
||||
#define REG_37_IN1R_TO_RIGHT_P_40k (3<<6)
|
||||
|
||||
#define REG_37_IN2R_TO_RIGHT_P_NO (0<<4)
|
||||
#define REG_37_IN2R_TO_RIGHT_P_10k (1<<4)
|
||||
#define REG_37_IN2R_TO_RIGHT_P_20k (2<<4)
|
||||
#define REG_37_IN2R_TO_RIGHT_P_40k (3<<4)
|
||||
|
||||
#define REG_37_IN3R_TO_RIGHT_P_NO (0<<2)
|
||||
#define REG_37_IN3R_TO_RIGHT_P_10k (1<<2)
|
||||
#define REG_37_IN3R_TO_RIGHT_P_20k (2<<2)
|
||||
#define REG_37_IN3R_TO_RIGHT_P_40k (3<<2)
|
||||
|
||||
#define REG_37_IN2L_TO_RIGHT_P_NO (0<<0)
|
||||
#define REG_37_IN2L_TO_RIGHT_P_10k (1<<0)
|
||||
#define REG_37_IN2L_TO_RIGHT_P_20k (2<<0)
|
||||
#define REG_37_IN2L_TO_RIGHT_P_40k (3<<0)
|
||||
|
||||
// Register - 0x01 / 0x39 (P1_R57): Right MICPGA Negative Terminal Input Routing Configuration
|
||||
#define REG_39_CM1R_TO_RIGHT_N_NO (0<<6)
|
||||
#define REG_39_CM1R_TO_RIGHT_N_10k (1<<6)
|
||||
#define REG_39_CM1R_TO_RIGHT_N_20k (2<<6)
|
||||
#define REG_39_CM1R_TO_RIGHT_N_40k (3<<6)
|
||||
|
||||
#define REG_39_IN1L_TO_RIGHT_N_NO (0<<4)
|
||||
#define REG_39_IN1L_TO_RIGHT_N_10k (1<<4)
|
||||
#define REG_39_IN1L_TO_RIGHT_N_20k (2<<4)
|
||||
#define REG_39_IN1L_TO_RIGHT_N_40k (3<<4)
|
||||
|
||||
#define REG_39_IN3L_TO_RIGHT_N_NO (0<<2)
|
||||
#define REG_39_IN3L_TO_RIGHT_N_10k (1<<2)
|
||||
#define REG_39_IN3L_TO_RIGHT_N_20k (2<<2)
|
||||
#define REG_39_IN3L_TO_RIGHT_N_40k (3<<2)
|
||||
|
||||
#define REG_39_CM2R_TO_RIGHT_N_NO (0<<0)
|
||||
#define REG_39_CM2R_TO_RIGHT_N_10k (1<<0)
|
||||
#define REG_39_CM2R_TO_RIGHT_N_20k (2<<0)
|
||||
#define REG_39_CM2R_TO_RIGHT_N_40k (3<<0)
|
||||
|
||||
static const uint8_t conf_data[] = {
|
||||
// reg, data,
|
||||
// PLL clock config
|
||||
|
|
@ -62,10 +146,10 @@ static const uint8_t conf_data[] = {
|
|||
0x0a, 0x33, /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */
|
||||
|
||||
0x3d, 0x00, /* Select ADC PTM_R4 */
|
||||
0x47, 0x32, /* Set MicPGA startup delay to 3.1ms */
|
||||
0x47, 0x32, /* Set MicPGA startup delay to 6.4ms */
|
||||
0x7b, 0x01, /* Set the REF charging time to 40ms */
|
||||
0x34, 0x10, /* Route IN2L to LEFT_P with 10K */
|
||||
0x36, 0x10, /* Route IN2R to LEFT_N with 10K */
|
||||
0x34, REG_34_IN2L_TO_LEFT_P_10k, /* Route IN2L to LEFT_P with 10K */
|
||||
0x36, REG_36_IN2R_TO_LEFT_N_10k, /* Route IN2R to LEFT_N with 10K */
|
||||
//0x37, 0x04, /* Route IN3R to RIGHT_P with 10K */
|
||||
//0x39, 0x04, /* Route IN3L to RIGHT_N with 10K */
|
||||
//0x3b, 0x00, /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */
|
||||
|
|
@ -82,15 +166,15 @@ static const uint8_t conf_data_unmute[] = {
|
|||
static const uint8_t conf_data_ch3_select[] = {
|
||||
// reg, data,
|
||||
0x00, 0x01, /* Select Page 1 */
|
||||
0x37, 0x04, /* Route IN3R to RIGHT_P with input impedance of 10K */
|
||||
0x39, 0x04, /* Route IN3L to RIGHT_N with input impedance of 10K */
|
||||
0x37, REG_37_IN3R_TO_RIGHT_P_10k, /* Route IN3R to RIGHT_P with input impedance of 10K */
|
||||
0x39, REG_39_IN3L_TO_RIGHT_N_10k, /* Route IN3L to RIGHT_N with input impedance of 10K */
|
||||
};
|
||||
|
||||
static const uint8_t conf_data_ch1_select[] = {
|
||||
// reg, data,
|
||||
0x00, 0x01, /* Select Page 1 */
|
||||
0x37, 0x40, /* Route IN1R to RIGHT_P with input impedance of 10K */
|
||||
0x39, 0x10, /* Route IN1L to RIGHT_N with input impedance of 10K */
|
||||
0x37, REG_37_IN1R_TO_RIGHT_P_10k, /* Route IN1R to RIGHT_P with input impedance of 10K */
|
||||
0x39, REG_39_IN1L_TO_RIGHT_N_10k, /* Route IN1L to RIGHT_N with input impedance of 10K */
|
||||
};
|
||||
|
||||
static inline void
|
||||
|
|
|
|||
23
ui.c
23
ui.c
|
|
@ -632,9 +632,10 @@ menu_transform_filter_cb(int item, uint8_t data)
|
|||
}
|
||||
|
||||
static void
|
||||
menu_bandwidth_cb(int item)
|
||||
menu_bandwidth_cb(int item, uint8_t data)
|
||||
{
|
||||
bandwidth = item;
|
||||
(void)item;
|
||||
bandwidth = data;
|
||||
draw_menu();
|
||||
}
|
||||
|
||||
|
|
@ -937,10 +938,10 @@ const menuitem_t menu_transform[] = {
|
|||
|
||||
const menuitem_t menu_bandwidth[] = {
|
||||
{ MT_CALLBACK, 0, "1 kHz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 0, "300 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 0, "100 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 0, "30 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 0, "10 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 1, "300 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 2, "100 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 3, "30 Hz", menu_bandwidth_cb },
|
||||
{ MT_CALLBACK, 4, "10 Hz", menu_bandwidth_cb },
|
||||
{ MT_CANCEL, 0, S_LARROW" BACK", NULL },
|
||||
{ MT_NONE, 0, NULL, NULL } // sentinel
|
||||
};
|
||||
|
|
@ -951,7 +952,7 @@ const menuitem_t menu_display[] = {
|
|||
{ MT_SUBMENU, 0, "SCALE", menu_scale },
|
||||
{ MT_SUBMENU, 0, "CHANNEL", menu_channel },
|
||||
{ MT_SUBMENU, 0, "TRANSFORM", menu_transform },
|
||||
{ MT_SUBMENU, 0, "BANDWIDTH", menu_bandwidth },
|
||||
{ MT_SUBMENU, 0, "BANDWIDTH", menu_bandwidth },
|
||||
{ MT_CANCEL, 0, S_LARROW" BACK", NULL },
|
||||
{ MT_NONE, 0, NULL, NULL } // sentinel
|
||||
};
|
||||
|
|
@ -1384,10 +1385,10 @@ menu_item_modify_attribute(const menuitem_t *menu, int item,
|
|||
*fg = config.menu_normal_color;
|
||||
}
|
||||
} else if (menu == menu_bandwidth) {
|
||||
if (item == bandwidth) {
|
||||
*bg = 0x0000;
|
||||
*fg = 0xffff;
|
||||
}
|
||||
if (item == bandwidth) {
|
||||
*bg = 0x0000;
|
||||
*fg = 0xffff;
|
||||
}
|
||||
} else if (menu == menu_transform) {
|
||||
if ((item == 0 && (domain_mode & DOMAIN_MODE) == DOMAIN_TIME)
|
||||
|| (item == 1 && (domain_mode & TD_FUNC) == TD_FUNC_LOWPASS_IMPULSE)
|
||||
|
|
|
|||
Loading…
Reference in a new issue