From 22e4df1577896ba11d79676349eb7efa9842d90e Mon Sep 17 00:00:00 2001 From: DiSlord Date: Sat, 21 Mar 2020 16:15:03 +0300 Subject: [PATCH] Little rework bandwidth: - Not reset sweep on request - Better menu response - little DSP optimization Faster i2c bus (now 600kHz, allow more faster add settings) Add i2c command (disabled by default) Little fix stat command --- dsp.c | 32 +++-- main.c | 309 +++++++++++++++++++++++++++--------------------- nanovna.h | 10 +- si5351.c | 2 +- tlv320aic3204.c | 98 +++++++++++++-- ui.c | 23 ++-- 6 files changed, 304 insertions(+), 170 deletions(-) diff --git a/dsp.c b/dsp.c index 4b616dc..b636b32 100644 --- a/dsp.c +++ b/dsp.c @@ -40,11 +40,27 @@ const int16_t sincos_tbl[48][2] = { { 32138, 6393 }, { 29389, -14493 }, { 14493, -29389 }, { -6393, -32138 }, {-24636, -21605 }, {-32698, -2143 }, {-27246, 18205 }, {-10533, 31029 } }; +#if 0 +void generate_DSP_Table(int offset){ + float audio_freq = 48000.0; + // N = offset * AUDIO_SAMPLES_COUNT / audio_freq; should be integer + // AUDIO_SAMPLES_COUNT = N * audio_freq / offset; N - minimum integer value for get integer SAMPLE_LEN + // Bandwidth on one step = audio_freq / AUDIO_SAMPLES_COUNT + float step = 2 * VNA_PI * offset / audio_freq; + float v = step/2; + for (int i=0; i>4; + samp_c += (smp * c)>>4; + ref_s += (ref * s)>>4; + ref_c += (ref * c)>>4; #if 0 uint32_t sc = *(uint32_t)&sincos_tbl[i]; samp_s = __SMLABB(sr, sc, samp_s); diff --git a/main.c b/main.c index 91f475c..e8fd058 100644 --- a/main.c +++ b/main.c @@ -70,6 +70,8 @@ static volatile vna_shellcmd_t shell_function = 0; // Enable color command, allow change config color for traces, grid, menu #define ENABLE_COLOR_COMMAND +//#define ENABLE_I2C_COMMAND + static void apply_error_term_at(int i); static void apply_edelay_at(int i); static void cal_interpolate(int s); @@ -88,6 +90,16 @@ static int8_t drive_strength = DRIVE_STRENGTH_AUTO; int8_t sweep_mode = SWEEP_ENABLE; volatile uint8_t redraw_request = 0; // contains REDRAW_XXX flags +// sweep operation variables +volatile uint8_t wait_count = 0; +static uint8_t accumerate_count = 0; + +static uint16_t p_sweep = 0; +// ChibiOS i2s buffer must be 2x size (for process one while next buffer filled by DMA) +static int16_t rx_buffer[AUDIO_BUFFER_LEN * 2]; +// Sweep measured data +float measured[2][POINTS_COUNT][2]; + // Version text, displayed in Config->Version menu, also send by info command const char *info_about[]={ BOARD_NAME, @@ -474,7 +486,9 @@ VNA_SHELL_FUNCTION(cmd_offset) shell_printf("usage: offset {frequency offset(Hz)}\r\n"); return; } - si5351_set_frequency_offset(my_atoi(argv[0])); + int32_t offset = my_atoi(argv[0]); +// generate_DSP_Table(offset); + si5351_set_frequency_offset(offset); } VNA_SHELL_FUNCTION(cmd_freq) @@ -577,94 +591,6 @@ static struct { #endif } stat; -int16_t rx_buffer[AUDIO_BUFFER_LEN * 2]; - -#ifdef ENABLED_DUMP -int16_t dump_buffer[AUDIO_BUFFER_LEN]; -int16_t dump_selection = 0; -#endif - -volatile uint8_t wait_count = 0; -volatile uint8_t accumerate_count = 0; - -const int8_t bandwidth_accumerate_count[] = { - 1, // 1kHz - 3, // 300Hz - 10, // 100Hz - 33, // 30Hz - 100 // 10Hz -}; - -float measured[2][POINTS_COUNT][2]; - -static inline void -dsp_start(int count) -{ - wait_count = count; - accumerate_count = bandwidth_accumerate_count[bandwidth]; - reset_dsp_accumerator(); -} - -static inline void -dsp_wait(void) -{ - while (accumerate_count > 0) - __WFI(); -} - -#ifdef ENABLED_DUMP -static void -duplicate_buffer_to_dump(int16_t *p) -{ - if (dump_selection == 1) - p = samp_buf; - else if (dump_selection == 2) - p = ref_buf; - memcpy(dump_buffer, p, sizeof dump_buffer); -} -#endif - -void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n) -{ -#if PORT_SUPPORTS_RT - int32_t cnt_s = port_rt_get_counter_value(); - int32_t cnt_e; -#endif - int16_t *p = &rx_buffer[offset]; - (void)i2sp; - (void)n; - - if (wait_count > 1) { - --wait_count; - } else if (wait_count > 0) { - if (accumerate_count > 0) { - dsp_process(p, n); - accumerate_count--; - } -#ifdef ENABLED_DUMP - duplicate_buffer_to_dump(p); -#endif - } - -#if PORT_SUPPORTS_RT - cnt_e = port_rt_get_counter_value(); - stat.interval_cycles = cnt_s - stat.last_counter_value; - stat.busy_cycles = cnt_e - cnt_s; - stat.last_counter_value = cnt_s; -#endif - stat.callback_count++; -} - -static const I2SConfig i2sconfig = { - NULL, // TX Buffer - rx_buffer, // RX Buffer - AUDIO_BUFFER_LEN * 2, - NULL, // tx callback - i2s_end_callback, // rx callback - 0, // i2scfgr - 2 // i2spr -}; - VNA_SHELL_FUNCTION(cmd_data) { int i; @@ -819,6 +745,7 @@ void load_default_properties(void) current_props._active_marker = 0; current_props._domain_mode = 0; current_props._marker_smith_format = MS_RLC; + current_props._bandwidth = 0; //Checksum add on caldata_save //current_props.checksum = 0; } @@ -835,45 +762,116 @@ ensure_edit_config(void) cal_status = 0; } +#ifdef ENABLED_DUMP +int16_t dump_buffer[AUDIO_BUFFER_LEN]; +int16_t dump_selection = 0; +#endif + +#ifdef ENABLED_DUMP +static void +duplicate_buffer_to_dump(int16_t *p) +{ + if (dump_selection == 1) + p = samp_buf; + else if (dump_selection == 2) + p = ref_buf; + memcpy(dump_buffer, p, sizeof dump_buffer); +} +#endif + +// +// DMA i2s callback function, called on get 'half' and 'full' buffer size data +// need for process data, while DMA fill next buffer +void i2s_end_callback(I2SDriver *i2sp, size_t offset, size_t n) +{ +#if PORT_SUPPORTS_RT + int32_t cnt_s = port_rt_get_counter_value(); + int32_t cnt_e; +#endif + int16_t *p = &rx_buffer[offset]; + (void)i2sp; + if (wait_count > 0){ + if (wait_count <= accumerate_count){ + if (wait_count == accumerate_count) + reset_dsp_accumerator(); + dsp_process(p, n); + } +#ifdef ENABLED_DUMP + duplicate_buffer_to_dump(p); +#endif + --wait_count; + } +#if PORT_SUPPORTS_RT + cnt_e = port_rt_get_counter_value(); + stat.interval_cycles = cnt_s - stat.last_counter_value; + stat.busy_cycles = cnt_e - cnt_s; + stat.last_counter_value = cnt_s; +#endif + stat.callback_count++; +} + +// Bandwidth depend from AUDIO_SAMPLES_COUNT and audio ADC frequency +// for AUDIO_SAMPLES_COUNT = 48 and ADC = 48kHz one measure give 48000/48=1000Hz +static const int8_t bandwidth_accumerate_count[] = { + 1, // 1kHz + 3, // 300Hz + 10, // 100Hz + 33, // 30Hz + 100 // 10Hz +}; + +static const I2SConfig i2sconfig = { + NULL, // TX Buffer + rx_buffer, // RX Buffer + sizeof(rx_buffer), // RX Buffer size + NULL, // tx callback + i2s_end_callback, // rx callback + 0, // i2scfgr + 0 // i2spr +}; + +#define DSP_START(delay) {accumerate_count = bandwidth_accumerate_count[bandwidth]; wait_count = delay-1 + accumerate_count;} +#define DSP_WAIT_READY while (wait_count) {if (operation_requested && break_on_operation) return false; __WFI();} +#define DSP_WAIT while (wait_count) {__WFI();} +#define RESET_SWEEP {p_sweep = 0;} #define DELAY_CHANNEL_CHANGE 2 // main loop for measurement bool sweep(bool break_on_operation) { - int i, delay; + int delay=1; + if (p_sweep>=sweep_points || break_on_operation == false) RESET_SWEEP; // blink LED while scanning palClearPad(GPIOC, GPIOC_LED); // Power stabilization after LED off, also align timings on i == 0 - for (i = 0; i < sweep_points; i++) { // 5300 - if (frequencies[i] == 0) break; - delay = set_frequency(frequencies[i]); // 700 + for (; p_sweep < sweep_points; p_sweep++) { // 5300 + if (frequencies[p_sweep] == 0) break; + delay+= set_frequency(frequencies[p_sweep]); tlv320aic3204_select(0); // 60 CH0:REFLECT, reset and begin measure - dsp_start(delay + ((i == 0) ? 1 : 0)); // 1900 + DSP_START(delay); + delay = 0; //================================================ // Place some code thats need execute while delay //================================================ - dsp_wait(); - // calculate reflection coefficient - (*sample_func)(measured[0][i]); // 60 + DSP_WAIT_READY; + (*sample_func)(measured[0][p_sweep]); // calculate reflection coefficient tlv320aic3204_select(1); // 60 CH1:TRANSMISSION, reset and begin measure - dsp_start(DELAY_CHANNEL_CHANGE); // 1700 + DSP_START(DELAY_CHANNEL_CHANGE); //================================================ // Place some code thats need execute while delay //================================================ - dsp_wait(); - // calculate transmission coefficient - (*sample_func)(measured[1][i]); // 60 + DSP_WAIT_READY; + (*sample_func)(measured[1][p_sweep]); // calculate transmission coefficient + // ======== 170 =========== if (cal_status & CALSTAT_APPLY) - apply_error_term_at(i); + apply_error_term_at(p_sweep); if (electrical_delay != 0) - apply_edelay_at(i); - - // back to toplevel to handle ui operation - if (operation_requested && break_on_operation) - return false; + apply_edelay_at(p_sweep); +// Display SPI made noise on measurement (can see in CW mode) +// ili9341_fill(OFFSETX+CELLOFFSETX, OFFSETY, (p_sweep * WIDTH)/(sweep_points-1), 1, RGB565(0,0,255)); } // blink LED while scanning palSetPad(GPIOC, GPIOC_LED); @@ -987,6 +985,7 @@ update_frequencies(void) // set grid layout update_grid(); + RESET_SWEEP; } void @@ -1537,7 +1536,7 @@ static const struct { const char *name; uint16_t refpos; float scale_unit; -} trace_info[] = { +} trace_info[MAX_TRACE_TYPE-1] = { { "LOGMAG", NGRIDY-1, 10.0 }, { "PHASE", NGRIDY/2, 90.0 }, { "DELAY", NGRIDY/2, 1e-9 }, @@ -1950,30 +1949,49 @@ VNA_SHELL_FUNCTION(cmd_stat) int16_t *p = &rx_buffer[0]; int32_t acc0, acc1; int32_t ave0, ave1; +// float sample[2], ref[2]; +// minr, maxr, mins, maxs; int32_t count = AUDIO_BUFFER_LEN; int i; (void)argc; (void)argv; - acc0 = acc1 = 0; - for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) { - acc0 += p[i]; - acc1 += p[i+1]; - } - ave0 = acc0 / count; - ave1 = acc1 / count; - acc0 = acc1 = 0; - for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) { - acc0 += (p[i] - ave0)*(p[i] - ave0); - acc1 += (p[i+1] - ave1)*(p[i+1] - ave1); - } - stat.rms[0] = sqrtf(acc0 / count); - stat.rms[1] = sqrtf(acc1 / count); - stat.ave[0] = ave0; - stat.ave[1] = ave1; + for (int ch=0;ch<2;ch++){ + tlv320aic3204_select(ch); + DSP_START(4); + DSP_WAIT; +// reset_dsp_accumerator(); +// dsp_process(&p[ 0], AUDIO_BUFFER_LEN); +// dsp_process(&p[AUDIO_BUFFER_LEN], AUDIO_BUFFER_LEN); - shell_printf("average: %d %d\r\n", stat.ave[0], stat.ave[1]); - shell_printf("rms: %d %d\r\n", stat.rms[0], stat.rms[1]); - shell_printf("callback count: %d\r\n", stat.callback_count); + acc0 = acc1 = 0; + for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) { + acc0 += p[i ]; + acc1 += p[i+1]; + } + ave0 = acc0 / count; + ave1 = acc1 / count; + acc0 = acc1 = 0; +// minr = maxr = 0; +// mins = maxs = 0; + for (i = 0; i < AUDIO_BUFFER_LEN*2; i += 2) { + acc0 += (p[i ] - ave0)*(p[i ] - ave0); + acc1 += (p[i+1] - ave1)*(p[i+1] - ave1); +// if (minr < p[i ]) minr = p[i ]; +// if (maxr > p[i ]) maxr = p[i ]; +// if (mins < p[i+1]) mins = p[i+1]; +// if (maxs > p[i+1]) maxs = p[i+1]; + } + stat.rms[0] = sqrtf(acc0 / count); + stat.rms[1] = sqrtf(acc1 / count); + stat.ave[0] = ave0; + stat.ave[1] = ave1; + shell_printf("Ch: %d\r\n", ch); + shell_printf("average: r: %6d s: %6d\r\n", stat.ave[0], stat.ave[1]); + shell_printf("rms: r: %6d s: %6d\r\n", stat.rms[0], stat.rms[1]); +// shell_printf("min: ref %6d ch %6d\r\n", minr, mins); +// shell_printf("max: ref %6d ch %6d\r\n", maxr, maxs); + } + //shell_printf("callback count: %d\r\n", stat.callback_count); //shell_printf("interval cycle: %d\r\n", stat.interval_cycles); //shell_printf("busy cycle: %d\r\n", stat.busy_cycles); //shell_printf("load: %d\r\n", stat.busy_cycles * 100 / stat.interval_cycles); @@ -2072,6 +2090,20 @@ VNA_SHELL_FUNCTION(cmd_color) } #endif +#ifdef ENABLE_I2C_COMMAND +VNA_SHELL_FUNCTION(cmd_i2c){ + uint8_t page = my_atoui(argv[0]); + uint8_t reg = my_atoui(argv[1]); + uint8_t data = my_atoui(argv[2]); + uint8_t d1[] = {0x00, page}; + uint8_t d2[] = { reg, data}; + i2cAcquireBus(&I2CD1); + (void)i2cMasterTransmitTimeout(&I2CD1, 0x18, d1, 2, NULL, 0, 1000); + (void)i2cMasterTransmitTimeout(&I2CD1, 0x18, d2, 2, NULL, 0, 1000); + i2cReleaseBus(&I2CD1); +} +#endif + #ifdef ENABLE_THREADS_COMMAND #if CH_CFG_USE_REGISTRY == FALSE #error "Threads Requite enabled CH_CFG_USE_REGISTRY in chconf.h" @@ -2121,7 +2153,7 @@ static const VNAShellCommand commands[] = {"version" , cmd_version , 0}, {"reset" , cmd_reset , 0}, {"freq" , cmd_freq , CMD_WAIT_MUTEX}, - {"offset" , cmd_offset , 0}, + {"offset" , cmd_offset , CMD_WAIT_MUTEX}, #ifdef ENABLE_TIME_COMMAND {"time" , cmd_time , 0}, #endif @@ -2134,8 +2166,8 @@ static const VNAShellCommand commands[] = #endif {"frequencies" , cmd_frequencies , 0}, {"port" , cmd_port , 0}, - {"stat" , cmd_stat , 0}, - {"gain" , cmd_gain , 0}, + {"stat" , cmd_stat , CMD_WAIT_MUTEX}, + {"gain" , cmd_gain , CMD_WAIT_MUTEX}, {"power" , cmd_power , 0}, {"sample" , cmd_sample , 0}, // {"gamma" , cmd_gamma , 0}, @@ -2166,6 +2198,9 @@ static const VNAShellCommand commands[] = #ifdef ENABLE_COLOR_COMMAND {"color" , cmd_color , 0}, #endif +#ifdef ENABLE_I2C_COMMAND + {"i2c" , cmd_i2c , CMD_WAIT_MUTEX}, +#endif #ifdef ENABLE_THREADS_COMMAND {"threads" , cmd_threads , 0}, #endif @@ -2307,13 +2342,13 @@ static const I2CConfig i2ccfg = { #elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK // STM32_I2C1SW == STM32_I2C1SW_SYSCLK (SYSCLK = 48MHz) // 400kHz @ SYSCLK 48MHz (Use 26.4.10 I2C_TIMINGR register configuration examples from STM32 RM0091 Reference manual) - STM32_TIMINGR_PRESC(5U) | - STM32_TIMINGR_SCLDEL(3U) | STM32_TIMINGR_SDADEL(3U) | - STM32_TIMINGR_SCLH(3U) | STM32_TIMINGR_SCLL(9U), +// STM32_TIMINGR_PRESC(5U) | +// STM32_TIMINGR_SCLDEL(3U) | STM32_TIMINGR_SDADEL(3U) | +// STM32_TIMINGR_SCLH(3U) | STM32_TIMINGR_SCLL(9U), // 600kHz @ SYSCLK 48MHz, manually get values, x1.5 I2C speed, but need calc timings -// STM32_TIMINGR_PRESC(3U) | -// STM32_TIMINGR_SCLDEL(2U) | STM32_TIMINGR_SDADEL(2U) | -// STM32_TIMINGR_SCLH(4U) | STM32_TIMINGR_SCLL(4U), + STM32_TIMINGR_PRESC(3U) | + STM32_TIMINGR_SCLDEL(2U) | STM32_TIMINGR_SDADEL(2U) | + STM32_TIMINGR_SCLH(4U) | STM32_TIMINGR_SCLL(4U), #else #error "Need Define STM32_I2C1SW and set correct TIMINGR settings" #endif @@ -2336,7 +2371,7 @@ int main(void) { halInit(); chSysInit(); - +// generate_DSP_Table(FREQUENCY_OFFSET); //palSetPadMode(GPIOB, 8, PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN); //palSetPadMode(GPIOB, 9, PAL_MODE_ALTERNATE(1) | PAL_STM32_OTYPE_OPENDRAIN); i2cStart(&I2CD1, &i2ccfg); diff --git a/nanovna.h b/nanovna.h index ec03e18..f9ddc17 100644 --- a/nanovna.h +++ b/nanovna.h @@ -104,12 +104,9 @@ extern const char *info_about[]; * dsp.c */ // 5ms @ 48kHz -#define AUDIO_BUFFER_LEN 96 - -extern int16_t rx_buffer[]; - -#define STATE_LEN 32 -#define SAMPLE_LEN 48 +#define AUDIO_SAMPLES_COUNT 48 +// Buffer contain left and right channel samples (need x2) +#define AUDIO_BUFFER_LEN (AUDIO_SAMPLES_COUNT*2) #ifdef ENABLED_DUMP extern int16_t ref_buf[]; @@ -121,6 +118,7 @@ void reset_dsp_accumerator(void); void calculate_gamma(float *gamma); void fetch_amplitude(float *gamma); void fetch_amplitude_ref(float *gamma); +void generate_DSP_Table(int offset); /* * tlv320aic3204.c diff --git a/si5351.c b/si5351.c index 8f7c9c5..b00274d 100644 --- a/si5351.c +++ b/si5351.c @@ -44,7 +44,7 @@ static int32_t current_offset = FREQUENCY_OFFSET; #define DELAY_NORMAL 2 // Delay for bands (depend set band 1 more fast (can change before next dsp buffer ready, need wait additional interval) #define DELAY_BAND_1 3 -#define DELAY_BAND_2 2 +#define DELAY_BAND_2 3 // Band changes need set delay after reset PLL #define DELAY_BANDCHANGE_1 3 #define DELAY_BANDCHANGE_2 3 diff --git a/tlv320aic3204.c b/tlv320aic3204.c index 21fbe84..3a33aff 100644 --- a/tlv320aic3204.c +++ b/tlv320aic3204.c @@ -25,6 +25,90 @@ #define wait_ms(ms) chThdSleepMilliseconds(ms) +// Register - 0x01 / 0x34 (P1_R52): Left MICPGA Positive Terminal Input Routing Configuration +#define REG_34_IN1L_TO_LEFT_P_NO (0<<6) +#define REG_34_IN1L_TO_LEFT_P_10k (1<<6) +#define REG_34_IN1L_TO_LEFT_P_20k (2<<6) +#define REG_34_IN1L_TO_LEFT_P_40k (3<<6) + +#define REG_34_IN2L_TO_LEFT_P_NO (0<<4) +#define REG_34_IN2L_TO_LEFT_P_10k (1<<4) +#define REG_34_IN2L_TO_LEFT_P_20k (2<<4) +#define REG_34_IN2L_TO_LEFT_P_40k (3<<4) + +#define REG_34_IN3L_TO_LEFT_P_NO (0<<2) +#define REG_34_IN3L_TO_LEFT_P_10k (1<<2) +#define REG_34_IN3L_TO_LEFT_P_20k (2<<2) +#define REG_34_IN3L_TO_LEFT_P_40k (3<<2) + +#define REG_34_IN1R_TO_LEFT_P_NO (0<<0) +#define REG_34_IN1R_TO_LEFT_P_10k (1<<0) +#define REG_34_IN1R_TO_LEFT_P_20k (2<<0) +#define REG_34_IN1R_TO_LEFT_P_40k (3<<0) + +// Register - 0x01 / 0x36 (P1_R54): Left MICPGA Negative Terminal Input Routing Configuration +#define REG_36_CM1L_TO_LEFT_N_NO (0<<6) +#define REG_36_CM1L_TO_LEFT_N_10k (1<<6) +#define REG_36_CM1L_TO_LEFT_N_20k (2<<6) +#define REG_36_CM1L_TO_LEFT_N_40k (3<<6) + +#define REG_36_IN2R_TO_LEFT_N_NO (0<<4) +#define REG_36_IN2R_TO_LEFT_N_10k (1<<4) +#define REG_36_IN2R_TO_LEFT_N_20k (2<<4) +#define REG_36_IN2R_TO_LEFT_N_40k (3<<4) + +#define REG_36_IN3R_TO_LEFT_N_NO (0<<2) +#define REG_36_IN3R_TO_LEFT_N_10k (1<<2) +#define REG_36_IN3R_TO_LEFT_N_20k (2<<2) +#define REG_36_IN3R_TO_LEFT_N_40k (3<<2) + +#define REG_36_CM2L_TO_LEFT_N_NO (0<<0) +#define REG_36_CM2L_TO_LEFT_N_10k (1<<0) +#define REG_36_CM2L_TO_LEFT_N_20k (2<<0) +#define REG_36_CM2L_TO_LEFT_N_40k (3<<0) + +// Register - 0x01 / 0x37 (P1_R55): Right MICPGA Positive Terminal Input Routing Configuration +#define REG_37_IN1R_TO_RIGHT_P_NO (0<<6) +#define REG_37_IN1R_TO_RIGHT_P_10k (1<<6) +#define REG_37_IN1R_TO_RIGHT_P_20k (2<<6) +#define REG_37_IN1R_TO_RIGHT_P_40k (3<<6) + +#define REG_37_IN2R_TO_RIGHT_P_NO (0<<4) +#define REG_37_IN2R_TO_RIGHT_P_10k (1<<4) +#define REG_37_IN2R_TO_RIGHT_P_20k (2<<4) +#define REG_37_IN2R_TO_RIGHT_P_40k (3<<4) + +#define REG_37_IN3R_TO_RIGHT_P_NO (0<<2) +#define REG_37_IN3R_TO_RIGHT_P_10k (1<<2) +#define REG_37_IN3R_TO_RIGHT_P_20k (2<<2) +#define REG_37_IN3R_TO_RIGHT_P_40k (3<<2) + +#define REG_37_IN2L_TO_RIGHT_P_NO (0<<0) +#define REG_37_IN2L_TO_RIGHT_P_10k (1<<0) +#define REG_37_IN2L_TO_RIGHT_P_20k (2<<0) +#define REG_37_IN2L_TO_RIGHT_P_40k (3<<0) + +// Register - 0x01 / 0x39 (P1_R57): Right MICPGA Negative Terminal Input Routing Configuration +#define REG_39_CM1R_TO_RIGHT_N_NO (0<<6) +#define REG_39_CM1R_TO_RIGHT_N_10k (1<<6) +#define REG_39_CM1R_TO_RIGHT_N_20k (2<<6) +#define REG_39_CM1R_TO_RIGHT_N_40k (3<<6) + +#define REG_39_IN1L_TO_RIGHT_N_NO (0<<4) +#define REG_39_IN1L_TO_RIGHT_N_10k (1<<4) +#define REG_39_IN1L_TO_RIGHT_N_20k (2<<4) +#define REG_39_IN1L_TO_RIGHT_N_40k (3<<4) + +#define REG_39_IN3L_TO_RIGHT_N_NO (0<<2) +#define REG_39_IN3L_TO_RIGHT_N_10k (1<<2) +#define REG_39_IN3L_TO_RIGHT_N_20k (2<<2) +#define REG_39_IN3L_TO_RIGHT_N_40k (3<<2) + +#define REG_39_CM2R_TO_RIGHT_N_NO (0<<0) +#define REG_39_CM2R_TO_RIGHT_N_10k (1<<0) +#define REG_39_CM2R_TO_RIGHT_N_20k (2<<0) +#define REG_39_CM2R_TO_RIGHT_N_40k (3<<0) + static const uint8_t conf_data[] = { // reg, data, // PLL clock config @@ -62,10 +146,10 @@ static const uint8_t conf_data[] = { 0x0a, 0x33, /* Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V */ 0x3d, 0x00, /* Select ADC PTM_R4 */ - 0x47, 0x32, /* Set MicPGA startup delay to 3.1ms */ + 0x47, 0x32, /* Set MicPGA startup delay to 6.4ms */ 0x7b, 0x01, /* Set the REF charging time to 40ms */ - 0x34, 0x10, /* Route IN2L to LEFT_P with 10K */ - 0x36, 0x10, /* Route IN2R to LEFT_N with 10K */ + 0x34, REG_34_IN2L_TO_LEFT_P_10k, /* Route IN2L to LEFT_P with 10K */ + 0x36, REG_36_IN2R_TO_LEFT_N_10k, /* Route IN2R to LEFT_N with 10K */ //0x37, 0x04, /* Route IN3R to RIGHT_P with 10K */ //0x39, 0x04, /* Route IN3L to RIGHT_N with 10K */ //0x3b, 0x00, /* Unmute Left MICPGA, Gain selection of 32dB to make channel gain 0dB */ @@ -82,15 +166,15 @@ static const uint8_t conf_data_unmute[] = { static const uint8_t conf_data_ch3_select[] = { // reg, data, 0x00, 0x01, /* Select Page 1 */ - 0x37, 0x04, /* Route IN3R to RIGHT_P with input impedance of 10K */ - 0x39, 0x04, /* Route IN3L to RIGHT_N with input impedance of 10K */ + 0x37, REG_37_IN3R_TO_RIGHT_P_10k, /* Route IN3R to RIGHT_P with input impedance of 10K */ + 0x39, REG_39_IN3L_TO_RIGHT_N_10k, /* Route IN3L to RIGHT_N with input impedance of 10K */ }; static const uint8_t conf_data_ch1_select[] = { // reg, data, 0x00, 0x01, /* Select Page 1 */ - 0x37, 0x40, /* Route IN1R to RIGHT_P with input impedance of 10K */ - 0x39, 0x10, /* Route IN1L to RIGHT_N with input impedance of 10K */ + 0x37, REG_37_IN1R_TO_RIGHT_P_10k, /* Route IN1R to RIGHT_P with input impedance of 10K */ + 0x39, REG_39_IN1L_TO_RIGHT_N_10k, /* Route IN1L to RIGHT_N with input impedance of 10K */ }; static inline void diff --git a/ui.c b/ui.c index 3e10a58..b22d1c8 100644 --- a/ui.c +++ b/ui.c @@ -632,9 +632,10 @@ menu_transform_filter_cb(int item, uint8_t data) } static void -menu_bandwidth_cb(int item) +menu_bandwidth_cb(int item, uint8_t data) { - bandwidth = item; + (void)item; + bandwidth = data; draw_menu(); } @@ -937,10 +938,10 @@ const menuitem_t menu_transform[] = { const menuitem_t menu_bandwidth[] = { { MT_CALLBACK, 0, "1 kHz", menu_bandwidth_cb }, - { MT_CALLBACK, 0, "300 Hz", menu_bandwidth_cb }, - { MT_CALLBACK, 0, "100 Hz", menu_bandwidth_cb }, - { MT_CALLBACK, 0, "30 Hz", menu_bandwidth_cb }, - { MT_CALLBACK, 0, "10 Hz", menu_bandwidth_cb }, + { MT_CALLBACK, 1, "300 Hz", menu_bandwidth_cb }, + { MT_CALLBACK, 2, "100 Hz", menu_bandwidth_cb }, + { MT_CALLBACK, 3, "30 Hz", menu_bandwidth_cb }, + { MT_CALLBACK, 4, "10 Hz", menu_bandwidth_cb }, { MT_CANCEL, 0, S_LARROW" BACK", NULL }, { MT_NONE, 0, NULL, NULL } // sentinel }; @@ -951,7 +952,7 @@ const menuitem_t menu_display[] = { { MT_SUBMENU, 0, "SCALE", menu_scale }, { MT_SUBMENU, 0, "CHANNEL", menu_channel }, { MT_SUBMENU, 0, "TRANSFORM", menu_transform }, - { MT_SUBMENU, 0, "BANDWIDTH", menu_bandwidth }, + { MT_SUBMENU, 0, "BANDWIDTH", menu_bandwidth }, { MT_CANCEL, 0, S_LARROW" BACK", NULL }, { MT_NONE, 0, NULL, NULL } // sentinel }; @@ -1384,10 +1385,10 @@ menu_item_modify_attribute(const menuitem_t *menu, int item, *fg = config.menu_normal_color; } } else if (menu == menu_bandwidth) { - if (item == bandwidth) { - *bg = 0x0000; - *fg = 0xffff; - } + if (item == bandwidth) { + *bg = 0x0000; + *fg = 0xffff; + } } else if (menu == menu_transform) { if ((item == 0 && (domain_mode & DOMAIN_MODE) == DOMAIN_TIME) || (item == 1 && (domain_mode & TD_FUNC) == TD_FUNC_LOWPASS_IMPULSE)