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Update defines
Allow select any ADC mode, add all settings for it
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DiSlord
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66bd2ae21a
commit
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39
nanovna.h
39
nanovna.h
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@ -36,17 +36,35 @@
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#define STOP_MAX 2700000000U
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// Frequency threshold (max frequency for si5351, harmonic mode after)
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#define FREQUENCY_THRESHOLD 300000100U
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// See AUDIO_ADC_FREQ settings, on change possible need adjust sweep timings in si5351.c for better speed
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// Frequency offset for 96k ADC (sin_cos table in dsp.c generated for 6k, 8k, 10k, 12k if change need create new table )
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#define FREQUENCY_OFFSET 8000
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// Frequency offset for 48k ADC (sin_cos table in dsp.c generated for 3k, 4k, 5k, 6k, if change need create new table )
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//#define FREQUENCY_OFFSET 5000
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// Define ADC sample rate (can be 48k, 96k, or 192k)
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//#define AUDIO_ADC_FREQ (192000)
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#define AUDIO_ADC_FREQ (96000)
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//#define AUDIO_ADC_FREQ (48000)
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// Frequency offset, depend from AUDIO_ADC_FREQ settings (need aligned table)
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// Use real time build table (undef for use constant, see comments)
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//#define USE_VARIABLE_OFFSET
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// For 192k ADC (sin_cos table in dsp.c generated for 8k, 12k if change need create new table )
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//#define FREQUENCY_OFFSET 8000
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#define FREQUENCY_OFFSET 12000
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// For 96k ADC (sin_cos table in dsp.c generated for 6k, 8k, 10k, 12k if change need create new table )
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//#define FREQUENCY_OFFSET 6000
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//#define FREQUENCY_OFFSET 8000
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//#define FREQUENCY_OFFSET 10000
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//#define FREQUENCY_OFFSET 12000
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// For 48k ADC (sin_cos table in dsp.c generated for 3k, 4k, 5k, 6k, if change need create new table )
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//#define FREQUENCY_OFFSET 3000
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//#define FREQUENCY_OFFSET 4000
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//#define FREQUENCY_OFFSET 5000
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//#define FREQUENCY_OFFSET 6000
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// Apply calibration after made sweep, (if set 1, then calibration move out from sweep cycle)
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#define APPLY_CALIBRATION_AFTER_SWEEP 0
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// Use real time build table (undef for use constant)
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//#define USE_VARIABLE_OFFSET
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// Speed of light const
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#define SPEED_OF_LIGHT 299792458
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// pi const
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#define VNA_PI 3.14159265358979323846
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@ -132,15 +150,12 @@ extern const char *info_about[];
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* dsp.c
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*/
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// Define aic3204 source clock frequency (on 8MHz used fractional multiplier, and possible little phase error)
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#define AUDIO_CLOCK_REF ( 8000000U)
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//#define AUDIO_CLOCK_REF ( 8000000U)
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// Define aic3204 source clock frequency (on 10752000U used integer multiplier)
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//#define AUDIO_CLOCK_REF (10752000U)
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#define AUDIO_CLOCK_REF (10752000U)
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// Disable AIC PLL clock, use input as CODEC_CLKIN (not stable on some devices, on long work)
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//#define AUDIO_CLOCK_REF (86016000U)
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// Define ADC sample rate
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#define AUDIO_ADC_FREQ (96000)
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//#define AUDIO_ADC_FREQ (48000)
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// Define sample count for one step measure
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#define AUDIO_SAMPLES_COUNT (48)
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// Buffer contain left and right channel samples (need x2)
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@ -154,8 +154,8 @@ static const uint8_t conf_data[] = {
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0x0e, 0x80, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power down
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0x12, 0x82, // Power up the NADC divider with value 2
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// ADC output sample rate depend from DAC, but internal use this settings
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0x12, 0x81, // Power up the NADC divider with value 1
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x80, // ADC Oversampling (AOSR) Program the OSR of ADC to 128
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0x3d, 0x01, // Select ADC PRB_R1
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@ -171,8 +171,27 @@ static const uint8_t conf_data[] = {
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0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 64
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0x0e, 0x40, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power up
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0x25, 0x00, // DAC power down
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// ADC output sample rate depend from DAC, but internal use this settings
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0x12, 0x81, // Power up the NADC divider with value 1
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x80, // ADC Oversampling (AOSR) set OSR of ADC to 128
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0x3d, 0x01, // Select ADC PRB_R1 (AOSR = 64 (Use with PRB_R1 to PRB_R12, ADC Filter Type A or B))
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0x24, 0xee, // ADC power up
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0x1b, 0x0c, // Set the BCLK,WCLK as output
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0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16)
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#elif AUDIO_ADC_FREQ == 192000
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// Clock config, default fs=192kHz
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// from PLL 86.016MHz/(2*7*32) = 192kHz
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// DAC setting, need only for set ADC sample rate output
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0x0b, 0x82, // Power up the NDAC divider with value 2
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0x0c, 0x87, // Power up the MDAC divider with value 7
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0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 32
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0x0e, 0x20, // DAC OSR Setting Register 2 (LSB)
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0x3c, 0x01, // Set the DAC Mode to PRB_P1
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0x25, 0x00, // DAC power down
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// ADC output sample rate depend from DAC, but internal use this settings
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0x12, 0x81, // Power up the NADC divider with value 1
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0x13, 0x87, // Power up the MADC divider with value 7
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0x14, 0x40, // ADC Oversampling (AOSR) set OSR of ADC to 64
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@ -180,7 +199,7 @@ static const uint8_t conf_data[] = {
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0x24, 0xee, // ADC power up
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0x1b, 0x0c, // Set the BCLK,WCLK as output
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0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16)
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0x1e, 0x80 + 7,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*7) = 192kHz * (16+16)
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#else
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#error "Need set correct ADC clock for aic3204"
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#endif
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@ -192,6 +211,7 @@ static const uint8_t conf_data[] = {
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0x7b, 0x01, // Set the REF charging time to 40ms
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0x14, 0x25, // HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
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0x0a, 0x33, // Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V
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// 0x0a, 0x40, // Set the Input Common Mode to 0.75V and Output Common Mode for Headphone to 1.65V
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0x3d, 0x00, // Select ADC PTM_R4 */
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// 0x3d, 0xB6, // Select ADC PTM_R2 */
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