diff --git a/nanovna.h b/nanovna.h index 85e0ba9..5d8afd1 100644 --- a/nanovna.h +++ b/nanovna.h @@ -36,17 +36,35 @@ #define STOP_MAX 2700000000U // Frequency threshold (max frequency for si5351, harmonic mode after) #define FREQUENCY_THRESHOLD 300000100U -// See AUDIO_ADC_FREQ settings, on change possible need adjust sweep timings in si5351.c for better speed -// Frequency offset for 96k ADC (sin_cos table in dsp.c generated for 6k, 8k, 10k, 12k if change need create new table ) -#define FREQUENCY_OFFSET 8000 -// Frequency offset for 48k ADC (sin_cos table in dsp.c generated for 3k, 4k, 5k, 6k, if change need create new table ) -//#define FREQUENCY_OFFSET 5000 + +// Define ADC sample rate (can be 48k, 96k, or 192k) +//#define AUDIO_ADC_FREQ (192000) +#define AUDIO_ADC_FREQ (96000) +//#define AUDIO_ADC_FREQ (48000) + +// Frequency offset, depend from AUDIO_ADC_FREQ settings (need aligned table) +// Use real time build table (undef for use constant, see comments) +//#define USE_VARIABLE_OFFSET +// For 192k ADC (sin_cos table in dsp.c generated for 8k, 12k if change need create new table ) +//#define FREQUENCY_OFFSET 8000 +#define FREQUENCY_OFFSET 12000 +// For 96k ADC (sin_cos table in dsp.c generated for 6k, 8k, 10k, 12k if change need create new table ) +//#define FREQUENCY_OFFSET 6000 +//#define FREQUENCY_OFFSET 8000 +//#define FREQUENCY_OFFSET 10000 +//#define FREQUENCY_OFFSET 12000 +// For 48k ADC (sin_cos table in dsp.c generated for 3k, 4k, 5k, 6k, if change need create new table ) +//#define FREQUENCY_OFFSET 3000 +//#define FREQUENCY_OFFSET 4000 +//#define FREQUENCY_OFFSET 5000 +//#define FREQUENCY_OFFSET 6000 + // Apply calibration after made sweep, (if set 1, then calibration move out from sweep cycle) #define APPLY_CALIBRATION_AFTER_SWEEP 0 -// Use real time build table (undef for use constant) -//#define USE_VARIABLE_OFFSET + // Speed of light const #define SPEED_OF_LIGHT 299792458 + // pi const #define VNA_PI 3.14159265358979323846 @@ -132,15 +150,12 @@ extern const char *info_about[]; * dsp.c */ // Define aic3204 source clock frequency (on 8MHz used fractional multiplier, and possible little phase error) -#define AUDIO_CLOCK_REF ( 8000000U) +//#define AUDIO_CLOCK_REF ( 8000000U) // Define aic3204 source clock frequency (on 10752000U used integer multiplier) -//#define AUDIO_CLOCK_REF (10752000U) +#define AUDIO_CLOCK_REF (10752000U) // Disable AIC PLL clock, use input as CODEC_CLKIN (not stable on some devices, on long work) //#define AUDIO_CLOCK_REF (86016000U) -// Define ADC sample rate -#define AUDIO_ADC_FREQ (96000) -//#define AUDIO_ADC_FREQ (48000) // Define sample count for one step measure #define AUDIO_SAMPLES_COUNT (48) // Buffer contain left and right channel samples (need x2) diff --git a/tlv320aic3204.c b/tlv320aic3204.c index e97bcd7..e82a163 100644 --- a/tlv320aic3204.c +++ b/tlv320aic3204.c @@ -154,8 +154,8 @@ static const uint8_t conf_data[] = { 0x0e, 0x80, // DAC OSR Setting Register 2 (LSB) 0x3c, 0x01, // Set the DAC Mode to PRB_P1 0x25, 0x00, // DAC power down - - 0x12, 0x82, // Power up the NADC divider with value 2 +// ADC output sample rate depend from DAC, but internal use this settings + 0x12, 0x81, // Power up the NADC divider with value 1 0x13, 0x87, // Power up the MADC divider with value 7 0x14, 0x80, // ADC Oversampling (AOSR) Program the OSR of ADC to 128 0x3d, 0x01, // Select ADC PRB_R1 @@ -171,8 +171,27 @@ static const uint8_t conf_data[] = { 0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 64 0x0e, 0x40, // DAC OSR Setting Register 2 (LSB) 0x3c, 0x01, // Set the DAC Mode to PRB_P1 - 0x25, 0x00, // DAC power up + 0x25, 0x00, // DAC power down +// ADC output sample rate depend from DAC, but internal use this settings + 0x12, 0x81, // Power up the NADC divider with value 1 + 0x13, 0x87, // Power up the MADC divider with value 7 + 0x14, 0x80, // ADC Oversampling (AOSR) set OSR of ADC to 128 + 0x3d, 0x01, // Select ADC PRB_R1 (AOSR = 64 (Use with PRB_R1 to PRB_R12, ADC Filter Type A or B)) + 0x24, 0xee, // ADC power up + 0x1b, 0x0c, // Set the BCLK,WCLK as output + 0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16) +#elif AUDIO_ADC_FREQ == 192000 +// Clock config, default fs=192kHz +// from PLL 86.016MHz/(2*7*32) = 192kHz +// DAC setting, need only for set ADC sample rate output + 0x0b, 0x82, // Power up the NDAC divider with value 2 + 0x0c, 0x87, // Power up the MDAC divider with value 7 + 0x0d, 0x00, // DAC OSR Setting Register 1 (MSB) Program the OSR of DAC to 32 + 0x0e, 0x20, // DAC OSR Setting Register 2 (LSB) + 0x3c, 0x01, // Set the DAC Mode to PRB_P1 + 0x25, 0x00, // DAC power down +// ADC output sample rate depend from DAC, but internal use this settings 0x12, 0x81, // Power up the NADC divider with value 1 0x13, 0x87, // Power up the MADC divider with value 7 0x14, 0x40, // ADC Oversampling (AOSR) set OSR of ADC to 64 @@ -180,7 +199,7 @@ static const uint8_t conf_data[] = { 0x24, 0xee, // ADC power up 0x1b, 0x0c, // Set the BCLK,WCLK as output - 0x1e, 0x80 + 14,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*14) = 96kHz * (16+16) + 0x1e, 0x80 + 7,// Enable the BCLKN divider with value 14 (I2S clock = 86.016MHz/(NDAC*7) = 192kHz * (16+16) #else #error "Need set correct ADC clock for aic3204" #endif @@ -192,6 +211,7 @@ static const uint8_t conf_data[] = { 0x7b, 0x01, // Set the REF charging time to 40ms 0x14, 0x25, // HP soft stepping settings for optimal pop performance at power up Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound. 0x0a, 0x33, // Set the Input Common Mode to 0.9V and Output Common Mode for Headphone to 1.65V +// 0x0a, 0x40, // Set the Input Common Mode to 0.75V and Output Common Mode for Headphone to 1.65V 0x3d, 0x00, // Select ADC PTM_R4 */ // 0x3d, 0xB6, // Select ADC PTM_R2 */