mirror of
https://github.com/ttrftech/NanoVNA.git
synced 2025-12-31 13:39:59 +01:00
fix unstable measurements (wait si5351 pll lock and voltage deviation from LED flashing)
This commit is contained in:
qrp73
parent
e81f4fe828
commit
23dba7d9b4
13
main.c
13
main.c
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@ -66,6 +66,10 @@ static THD_FUNCTION(Thread1, arg)
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chRegSetThreadName("sweep");
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while (1) {
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// disable led and wait for voltage stabilization
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palClearPad(GPIOC, GPIOC_LED);
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chThdSleepMilliseconds(10);
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bool completed = false;
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if (sweep_enabled || sweep_once) {
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chMtxLock(&mutex);
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@ -76,6 +80,9 @@ static THD_FUNCTION(Thread1, arg)
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__WFI();
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}
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// enable led
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palSetPad(GPIOC, GPIOC_LED);
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chMtxLock(&mutex);
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ui_process();
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@ -655,9 +662,6 @@ bool sweep(bool break_on_operation)
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tlv320aic3204_select_in3(); // CH0:REFLECT
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wait_dsp(delay);
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// blink LED while scanning
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palClearPad(GPIOC, GPIOC_LED);
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/* calculate reflection coeficient */
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(*sample_func)(measured[0][i]);
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@ -667,9 +671,6 @@ bool sweep(bool break_on_operation)
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/* calculate transmission coeficient */
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(*sample_func)(measured[1][i]);
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// blink LED while scanning
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palSetPad(GPIOC, GPIOC_LED);
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if (cal_status & CALSTAT_APPLY)
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apply_error_term_at(i);
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@ -117,7 +117,8 @@
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#define STM32_I2C_BUSY_TIMEOUT 50
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#define STM32_I2C_I2C1_IRQ_PRIORITY 3
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#define STM32_I2C_I2C2_IRQ_PRIORITY 3
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#define STM32_I2C_USE_DMA TRUE
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// note: for unknown reason I2C read operation doesn't works with USE_DMA=TRUE
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#define STM32_I2C_USE_DMA FALSE
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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79
si5351.c
79
si5351.c
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@ -22,8 +22,16 @@
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#define SI5351_I2C_ADDR (0x60<<1)
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static void
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si5351_write(uint8_t reg, uint8_t dat)
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static bool si5351_bulk_read(uint8_t reg, uint8_t* buf, int len)
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{
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int addr = SI5351_I2C_ADDR>>1;
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i2cAcquireBus(&I2CD1);
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msg_t mr = i2cMasterTransmitTimeout(&I2CD1, addr, ®, 1, buf, len, 1000);
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i2cReleaseBus(&I2CD1);
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return mr == MSG_OK;
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}
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static void si5351_write(uint8_t reg, uint8_t dat)
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{
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int addr = SI5351_I2C_ADDR>>1;
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uint8_t buf[] = { reg, dat };
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@ -32,8 +40,7 @@ si5351_write(uint8_t reg, uint8_t dat)
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i2cReleaseBus(&I2CD1);
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}
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static void
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si5351_bulk_write(const uint8_t *buf, int len)
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static void si5351_bulk_write(const uint8_t *buf, int len)
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{
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int addr = SI5351_I2C_ADDR>>1;
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i2cAcquireBus(&I2CD1);
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@ -57,9 +64,31 @@ const uint8_t si5351_configs[] = {
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0 // sentinel
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};
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void
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si5351_init(void)
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void si5351_wait_ready()
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{
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uint8_t status = 0xff;
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do
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{
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// if comm timeout, then wait infinite
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if(!si5351_bulk_read(0, &status, 1))
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status = 0xff;
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} while ((status & 0x80) != 0);
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}
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void si5351_wait_pll_lock()
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{
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uint8_t status = 0xff;
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do
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{
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// if comm timeout, then wait infinite
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if(!si5351_bulk_read(0, &status, 1))
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status = 0xff;
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} while ((status & 0x60) != 0);
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}
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void si5351_init(void)
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{
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si5351_wait_ready();
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const uint8_t *p = si5351_configs;
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while (*p) {
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uint8_t len = *p++;
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@ -146,14 +175,14 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */
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si5351_bulk_write(reg, 9);
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}
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void
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si5351_setupMultisynth(uint8_t output,
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uint8_t pllSource,
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uint32_t div, // 4,6,8, 8+ ~ 900
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uint32_t num,
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uint32_t denom,
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uint32_t rdiv, // SI5351_R_DIV_1~128
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uint8_t drive_strength)
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void si5351_setupMultisynth(
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uint8_t output,
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uint8_t pllSource,
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uint32_t div, // 4,6,8, 8+ ~ 900
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uint32_t num,
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uint32_t denom,
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uint32_t rdiv, // SI5351_R_DIV_1~128
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uint8_t drive_strength)
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{
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/* Get the appropriate starting point for the PLL registers */
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const uint8_t msreg_base[] = {
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@ -221,8 +250,7 @@ si5351_setupMultisynth(uint8_t output,
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si5351_write(clkctrl[output], dat);
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}
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static uint32_t
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gcd(uint32_t x, uint32_t y)
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static uint32_t gcd(uint32_t x, uint32_t y)
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{
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uint32_t z;
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while (y != 0) {
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@ -237,9 +265,9 @@ gcd(uint32_t x, uint32_t y)
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#define PLL_N 32
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#define PLLFREQ (XTALFREQ * PLL_N)
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void
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si5351_set_frequency_fixedpll(int channel, int pll, int pllfreq, int freq,
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uint32_t rdiv, uint8_t drive_strength)
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void si5351_set_frequency_fixedpll(
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int channel, int pll, int pllfreq, int freq,
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uint32_t rdiv, uint8_t drive_strength)
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{
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int32_t div = pllfreq / freq; // range: 8 ~ 1800
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int32_t num = pllfreq - freq * div;
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@ -255,9 +283,9 @@ si5351_set_frequency_fixedpll(int channel, int pll, int pllfreq, int freq,
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si5351_setupMultisynth(channel, pll, div, num, denom, rdiv, drive_strength);
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}
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void
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si5351_set_frequency_fixeddiv(int channel, int pll, int freq, int div,
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uint8_t drive_strength)
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void si5351_set_frequency_fixeddiv(
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int channel, int pll, int freq, int div,
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uint8_t drive_strength)
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{
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int32_t pllfreq = freq * div;
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int32_t multi = pllfreq / XTALFREQ;
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@ -279,8 +307,7 @@ si5351_set_frequency_fixeddiv(int channel, int pll, int freq, int div,
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* 100~150MHz fractional PLL 600-900MHz, fixed divider 6
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* 150~200MHz fractional PLL 600-900MHz, fixed divider 4
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*/
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void
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si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
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void si5351_set_frequency(int channel, int freq, uint8_t drive_strength)
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{
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if (freq <= 100000000) {
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si5351_setupPLL(SI5351_PLL_B, 32, 0, 1);
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@ -302,8 +329,7 @@ int current_band = -1;
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* CLK2: fixed 8MHz
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*/
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#define CLK2_FREQUENCY 8000000L
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int
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si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
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int si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
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{
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int band;
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int delay = 3;
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@ -385,6 +411,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
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if (current_band != band) {
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si5351_reset_pll();
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si5351_wait_pll_lock();
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#if 1
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si5351_enable_output();
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#endif
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