diff --git a/main.c b/main.c index 91cc8a3..0b622ee 100644 --- a/main.c +++ b/main.c @@ -66,6 +66,10 @@ static THD_FUNCTION(Thread1, arg) chRegSetThreadName("sweep"); while (1) { + // disable led and wait for voltage stabilization + palClearPad(GPIOC, GPIOC_LED); + chThdSleepMilliseconds(10); + bool completed = false; if (sweep_enabled || sweep_once) { chMtxLock(&mutex); @@ -76,6 +80,9 @@ static THD_FUNCTION(Thread1, arg) __WFI(); } + // enable led + palSetPad(GPIOC, GPIOC_LED); + chMtxLock(&mutex); ui_process(); @@ -655,9 +662,6 @@ bool sweep(bool break_on_operation) tlv320aic3204_select_in3(); // CH0:REFLECT wait_dsp(delay); - // blink LED while scanning - palClearPad(GPIOC, GPIOC_LED); - /* calculate reflection coeficient */ (*sample_func)(measured[0][i]); @@ -667,9 +671,6 @@ bool sweep(bool break_on_operation) /* calculate transmission coeficient */ (*sample_func)(measured[1][i]); - // blink LED while scanning - palSetPad(GPIOC, GPIOC_LED); - if (cal_status & CALSTAT_APPLY) apply_error_term_at(i); diff --git a/mcuconf.h b/mcuconf.h index 773537f..a38aaaf 100644 --- a/mcuconf.h +++ b/mcuconf.h @@ -117,7 +117,8 @@ #define STM32_I2C_BUSY_TIMEOUT 50 #define STM32_I2C_I2C1_IRQ_PRIORITY 3 #define STM32_I2C_I2C2_IRQ_PRIORITY 3 -#define STM32_I2C_USE_DMA TRUE +// note: for unknown reason I2C read operation doesn't works with USE_DMA=TRUE +#define STM32_I2C_USE_DMA FALSE #define STM32_I2C_I2C1_DMA_PRIORITY 1 #define STM32_I2C_I2C2_DMA_PRIORITY 1 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) diff --git a/si5351.c b/si5351.c index ebd4aa9..c2d61de 100644 --- a/si5351.c +++ b/si5351.c @@ -22,8 +22,16 @@ #define SI5351_I2C_ADDR (0x60<<1) -static void -si5351_write(uint8_t reg, uint8_t dat) +static bool si5351_bulk_read(uint8_t reg, uint8_t* buf, int len) +{ + int addr = SI5351_I2C_ADDR>>1; + i2cAcquireBus(&I2CD1); + msg_t mr = i2cMasterTransmitTimeout(&I2CD1, addr, ®, 1, buf, len, 1000); + i2cReleaseBus(&I2CD1); + return mr == MSG_OK; +} + +static void si5351_write(uint8_t reg, uint8_t dat) { int addr = SI5351_I2C_ADDR>>1; uint8_t buf[] = { reg, dat }; @@ -32,8 +40,7 @@ si5351_write(uint8_t reg, uint8_t dat) i2cReleaseBus(&I2CD1); } -static void -si5351_bulk_write(const uint8_t *buf, int len) +static void si5351_bulk_write(const uint8_t *buf, int len) { int addr = SI5351_I2C_ADDR>>1; i2cAcquireBus(&I2CD1); @@ -57,9 +64,31 @@ const uint8_t si5351_configs[] = { 0 // sentinel }; -void -si5351_init(void) +void si5351_wait_ready() { + uint8_t status = 0xff; + do + { + // if comm timeout, then wait infinite + if(!si5351_bulk_read(0, &status, 1)) + status = 0xff; + } while ((status & 0x80) != 0); +} + +void si5351_wait_pll_lock() +{ + uint8_t status = 0xff; + do + { + // if comm timeout, then wait infinite + if(!si5351_bulk_read(0, &status, 1)) + status = 0xff; + } while ((status & 0x60) != 0); +} + +void si5351_init(void) +{ + si5351_wait_ready(); const uint8_t *p = si5351_configs; while (*p) { uint8_t len = *p++; @@ -146,14 +175,14 @@ void si5351_setupPLL(uint8_t pll, /* SI5351_PLL_A or SI5351_PLL_B */ si5351_bulk_write(reg, 9); } -void -si5351_setupMultisynth(uint8_t output, - uint8_t pllSource, - uint32_t div, // 4,6,8, 8+ ~ 900 - uint32_t num, - uint32_t denom, - uint32_t rdiv, // SI5351_R_DIV_1~128 - uint8_t drive_strength) +void si5351_setupMultisynth( + uint8_t output, + uint8_t pllSource, + uint32_t div, // 4,6,8, 8+ ~ 900 + uint32_t num, + uint32_t denom, + uint32_t rdiv, // SI5351_R_DIV_1~128 + uint8_t drive_strength) { /* Get the appropriate starting point for the PLL registers */ const uint8_t msreg_base[] = { @@ -221,8 +250,7 @@ si5351_setupMultisynth(uint8_t output, si5351_write(clkctrl[output], dat); } -static uint32_t -gcd(uint32_t x, uint32_t y) +static uint32_t gcd(uint32_t x, uint32_t y) { uint32_t z; while (y != 0) { @@ -237,9 +265,9 @@ gcd(uint32_t x, uint32_t y) #define PLL_N 32 #define PLLFREQ (XTALFREQ * PLL_N) -void -si5351_set_frequency_fixedpll(int channel, int pll, int pllfreq, int freq, - uint32_t rdiv, uint8_t drive_strength) +void si5351_set_frequency_fixedpll( + int channel, int pll, int pllfreq, int freq, + uint32_t rdiv, uint8_t drive_strength) { int32_t div = pllfreq / freq; // range: 8 ~ 1800 int32_t num = pllfreq - freq * div; @@ -255,9 +283,9 @@ si5351_set_frequency_fixedpll(int channel, int pll, int pllfreq, int freq, si5351_setupMultisynth(channel, pll, div, num, denom, rdiv, drive_strength); } -void -si5351_set_frequency_fixeddiv(int channel, int pll, int freq, int div, - uint8_t drive_strength) +void si5351_set_frequency_fixeddiv( + int channel, int pll, int freq, int div, + uint8_t drive_strength) { int32_t pllfreq = freq * div; int32_t multi = pllfreq / XTALFREQ; @@ -279,8 +307,7 @@ si5351_set_frequency_fixeddiv(int channel, int pll, int freq, int div, * 100~150MHz fractional PLL 600-900MHz, fixed divider 6 * 150~200MHz fractional PLL 600-900MHz, fixed divider 4 */ -void -si5351_set_frequency(int channel, int freq, uint8_t drive_strength) +void si5351_set_frequency(int channel, int freq, uint8_t drive_strength) { if (freq <= 100000000) { si5351_setupPLL(SI5351_PLL_B, 32, 0, 1); @@ -302,8 +329,7 @@ int current_band = -1; * CLK2: fixed 8MHz */ #define CLK2_FREQUENCY 8000000L -int -si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength) +int si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength) { int band; int delay = 3; @@ -385,6 +411,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength) if (current_band != band) { si5351_reset_pll(); + si5351_wait_pll_lock(); #if 1 si5351_enable_output(); #endif