ttrftech/NanoVNA
1
0
Fork 0
mirror of https://github.com/ttrftech/NanoVNA.git synced 2025-12-06 03:31:59 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

feat: extend to 900MHz

Browse source
This commit is contained in:
TT 2019-07-25 06:23:27 +09:00
parent 9681d9b45d
commit 10a58f9580
2 changed files with 8 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
main.c
View file

@ -587,7 +587,7 @@ freq_mode_centerspan(void)
#define START_MIN 50000
#define STOP_MAX 300000000
#define STOP_MAX 900000000
void
set_sweep_frequency(int type, float frequency)

10
si5351.c
View file

@ -309,6 +309,10 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
int delay = 5;
uint32_t ofreq = freq + offset;
uint32_t rdiv = SI5351_R_DIV_1;
if (freq > 300000000) {
freq /= 3;
ofreq /= 5;
}
if (freq <= 100000000) {
band = 0;
} else if (freq < 150000000) {
@ -356,13 +360,13 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
case 1:
// Set PLL twice on changing from band 2
if (current_band == 2) {
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
}
// div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 6, CLK2_FREQUENCY,
@ -374,7 +378,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 4, drive_strength);
si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 4, CLK2_FREQUENCY,
SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 4,
si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 4,
SI5351_CLK_DRIVE_STRENGTH_2MA);
break;
}