diff --git a/main.c b/main.c
index 6d814fd..366f108 100644
--- a/main.c
+++ b/main.c
@@ -587,7 +587,7 @@ freq_mode_centerspan(void)
 
 
 #define START_MIN 50000
-#define STOP_MAX 300000000
+#define STOP_MAX 900000000
 
 void
 set_sweep_frequency(int type, float frequency)
diff --git a/si5351.c b/si5351.c
index e314cd4..89e7121 100644
--- a/si5351.c
+++ b/si5351.c
@@ -309,6 +309,10 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
   int delay = 5;
   uint32_t ofreq = freq + offset;
   uint32_t rdiv = SI5351_R_DIV_1;
+  if (freq > 300000000) {
+    freq /= 3;
+    ofreq /= 5;
+  }
   if (freq <= 100000000) {
     band = 0;
   } else if (freq < 150000000) {
@@ -356,13 +360,13 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
   case 1:
     // Set PLL twice on changing from band 2
     if (current_band == 2) {
-      si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
+      si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
                                     SI5351_CLK_DRIVE_STRENGTH_2MA);
       si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
     }
 
     // div by 6 mode. both PLL A and B are dedicated for CLK0, CLK1
-    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 6,
+    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 6,
                                   SI5351_CLK_DRIVE_STRENGTH_2MA);
     si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 6, drive_strength);
     si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 6, CLK2_FREQUENCY,
@@ -374,7 +378,7 @@ si5351_set_frequency_with_offset(int freq, int offset, uint8_t drive_strength)
     si5351_set_frequency_fixeddiv(1, SI5351_PLL_B, freq, 4, drive_strength);
     si5351_set_frequency_fixedpll(2, SI5351_PLL_B, freq * 4, CLK2_FREQUENCY,
                                   SI5351_R_DIV_1, SI5351_CLK_DRIVE_STRENGTH_2MA);
-    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, freq + offset, 4,
+    si5351_set_frequency_fixeddiv(0, SI5351_PLL_A, ofreq, 4,
                                   SI5351_CLK_DRIVE_STRENGTH_2MA);
     break;
   }