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https://github.com/ttrftech/NanoVNA.git
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project files
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parent
0ad69b4496
commit
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8
.gitignore
vendored
8
.gitignore
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@ -8,4 +8,10 @@ python
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*.py
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*.py
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*.ipynb
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*.ipynb
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TAGS
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TAGS
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.emacs-dirvars
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.emacs-dirvars
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iar/Debug
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iar/Release
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iar/settings
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*.dep
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*.ewd
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*.ewt
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42
NANOVNA_STM32_F072/ch.icf
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42
NANOVNA_STM32_F072/ch.icf
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x08000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
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define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0x400;
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/**** End of ICF editor section. ###ICF###*/
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/* Size of the IRQ Stack (Main Stack).*/
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define symbol __ICFEDIT_size_irqstack__ = 0x400;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK};
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define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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define block SYSHEAP with alignment = 8 {section SYSHEAP};
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define block DATABSS with alignment = 8 {readwrite, zeroinit};
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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keep { section .intvec };
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place at address mem:__ICFEDIT_intvec_start__ {section .intvec};
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place in ROM_region {readonly};
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place at start of RAM_region {block IRQSTACK};
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place in RAM_region {block DATABSS, block HEAP};
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place in RAM_region {block SYSHEAP};
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place at end of RAM_region {block CSTACK};
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export symbol __ICFEDIT_region_RAM_start__;
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export symbol __ICFEDIT_region_RAM_end__;
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2409
iar/NanoVNA.ewp
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2409
iar/NanoVNA.ewp
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File diff suppressed because it is too large
Load diff
7
iar/NanoVNA.eww
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7
iar/NanoVNA.eww
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<?xml version="1.0" encoding="UTF-8"?>
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<workspace>
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<project>
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<path>$WS_DIR$\NanoVNA.ewp</path>
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</project>
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<batchBuild />
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</workspace>
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