diff --git a/.gitignore b/.gitignore
index 42c4b55..a1f4427 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,4 +8,10 @@ python
*.py
*.ipynb
TAGS
-.emacs-dirvars
\ No newline at end of file
+.emacs-dirvars
+iar/Debug
+iar/Release
+iar/settings
+*.dep
+*.ewd
+*.ewt
\ No newline at end of file
diff --git a/NANOVNA_STM32_F072/ch.icf b/NANOVNA_STM32_F072/ch.icf
new file mode 100644
index 0000000..b4586f2
--- /dev/null
+++ b/NANOVNA_STM32_F072/ch.icf
@@ -0,0 +1,42 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+/* Size of the IRQ Stack (Main Stack).*/
+define symbol __ICFEDIT_size_irqstack__ = 0x400;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ {section CSTACK};
+define block IRQSTACK with alignment = 8, size = __ICFEDIT_size_irqstack__ {};
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+define block SYSHEAP with alignment = 8 {section SYSHEAP};
+define block DATABSS with alignment = 8 {readwrite, zeroinit};
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+keep { section .intvec };
+
+place at address mem:__ICFEDIT_intvec_start__ {section .intvec};
+place in ROM_region {readonly};
+place at start of RAM_region {block IRQSTACK};
+place in RAM_region {block DATABSS, block HEAP};
+place in RAM_region {block SYSHEAP};
+place at end of RAM_region {block CSTACK};
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
\ No newline at end of file
diff --git a/iar/NanoVNA.ewp b/iar/NanoVNA.ewp
new file mode 100644
index 0000000..853e9f2
--- /dev/null
+++ b/iar/NanoVNA.ewp
@@ -0,0 +1,2409 @@
+
+
+ 3
+
+ Debug
+
+ ARM
+
+ 1
+
+ General
+ 3
+
+ 29
+ 1
+ 1
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 34
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 10
+ 1
+ 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 1
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+ 0
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 20
+ 1
+ 1
+
+
+
+
+
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+
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+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 1
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ Release
+
+ ARM
+
+ 0
+
+ General
+ 3
+
+ 29
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ICCARM
+ 2
+
+ 34
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AARM
+ 2
+
+ 10
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ OBJCOPY
+ 0
+
+ 1
+ 1
+ 0
+
+
+
+
+
+
+
+
+ CUSTOM
+ 3
+
+
+
+ 0
+
+
+
+ BICOMP
+ 0
+
+
+
+ BUILDACTION
+ 1
+
+
+
+
+
+
+ ILINK
+ 0
+
+ 20
+ 1
+ 0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ IARCHIVE
+ 0
+
+ 0
+ 1
+ 0
+
+
+
+
+
+
+ BILINK
+ 0
+
+
+
+
+ src
+
+ ChibiOS
+
+ os
+
+ common
+
+ ports
+
+ ARMCMx
+
+ compilers
+
+ $PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\compilers\IAR\chcoreasm_v6m.s
+
+
+
+ $PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\chcore.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\common\ports\ARMCMx\chcore_v6m.c
+
+
+
+
+ startup
+
+ ARMCMx
+
+ compilers
+
+ $PROJ_DIR$\..\ChibiOS\os\common\startup\ARMCMx\compilers\IAR\cstartup.s
+
+
+ $PROJ_DIR$\..\ChibiOS\os\common\startup\ARMCMx\compilers\IAR\vectors.s
+
+
+
+
+
+
+ hal
+
+ lib
+
+ streams
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\chprintf.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\lib\streams\memstreams.c
+
+
+
+
+ ports
+
+ common
+
+ ARMCMx
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\common\ARMCMx\nvic.c
+
+
+
+
+ STM32
+
+ LLD
+
+ DACv1
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DACv1\hal_dac_lld.c
+
+
+
+ DMAv1
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\DMAv1\stm32_dma.c
+
+
+
+ EXTIv1
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\EXTIv1\hal_ext_lld.c
+
+
+
+ GPIOv2
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\GPIOv2\hal_pal_lld.c
+
+
+
+ I2Cv2
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\I2Cv2\hal_i2c_lld.c
+
+
+
+ RTCv2
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\RTCv2\hal_rtc_lld.c
+
+
+
+ SPIv2
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv2\hal_i2s_lld.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\SPIv2\hal_spi_lld.c
+
+
+
+ TIMv1
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\hal_gpt_lld.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\TIMv1\hal_st_lld.c
+
+
+
+ USARTv2
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USARTv2\hal_serial_lld.c
+
+
+
+ USBv1
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\LLD\USBv1\hal_usb_lld.c
+
+
+
+
+ STM32F0xx
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F0xx\hal_ext_lld_isr.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\ports\STM32\STM32F0xx\hal_lld.c
+
+
+
+
+
+ src
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_buffers.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_dac.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_ext.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_gpt.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_i2c.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_i2s.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_queues.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_rtc.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_serial.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_serial_usb.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_spi.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_st.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\hal\src\hal_usb.c
+
+
+
+
+ rt
+
+ src
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chevents.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chmtx.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chregistry.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chschd.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chsys.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chthreads.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\rt\src\chvt.c
+
+
+
+
+ various
+
+ shell
+
+ $PROJ_DIR$\..\ChibiOS\os\various\shell\shell.c
+
+
+ $PROJ_DIR$\..\ChibiOS\os\various\shell\shell_cmd.c
+
+
+
+
+
+
+ header
+
+ $PROJ_DIR$\..\bin2hex.h
+
+
+ $PROJ_DIR$\..\chconf.h
+
+
+ $PROJ_DIR$\..\ffconf.h
+
+
+ $PROJ_DIR$\..\fft.h
+
+
+ $PROJ_DIR$\..\halconf.h
+
+
+ $PROJ_DIR$\..\mcuconf.h
+
+
+ $PROJ_DIR$\..\nanovna.h
+
+
+ $PROJ_DIR$\..\si5351.h
+
+
+ $PROJ_DIR$\..\usbcfg.h
+
+
+
+ NANOVNA_STM32_F072
+
+ $PROJ_DIR$\..\NANOVNA_STM32_F072\board.c
+
+
+ $PROJ_DIR$\..\NANOVNA_STM32_F072\ch.icf
+
+
+
+ $PROJ_DIR$\..\adc.c
+
+
+ $PROJ_DIR$\..\dsp.c
+
+
+ $PROJ_DIR$\..\flash.c
+
+
+ $PROJ_DIR$\..\Font5x7.c
+
+
+ $PROJ_DIR$\..\ili9341.c
+
+
+ $PROJ_DIR$\..\main.c
+
+
+ $PROJ_DIR$\..\numfont20x24.c
+
+
+ $PROJ_DIR$\..\plot.c
+
+
+ $PROJ_DIR$\..\si5351.c
+
+
+ $PROJ_DIR$\..\tlv320aic3204.c
+
+
+ $PROJ_DIR$\..\ui.c
+
+
+ $PROJ_DIR$\..\usbcfg.c
+
+
+
diff --git a/iar/NanoVNA.eww b/iar/NanoVNA.eww
new file mode 100644
index 0000000..9c190ea
--- /dev/null
+++ b/iar/NanoVNA.eww
@@ -0,0 +1,7 @@
+
+
+
+ $WS_DIR$\NanoVNA.ewp
+
+
+