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6c06293179
Adds ability to set phase adjustment on Source PLL for each sweep point. When sourcePhase != 0, the FPGA executes a CDM toggle sequence after normal PLL register load to apply the specified phase offset. Changes: - MAX2871.vhd: add PHASE_ADJUST input and CDM toggle state machine - Sweep.vhd: extract phase from config, generate phase adjust signal - SPIConfig.vhd: handle 112-bit config data (was 96-bit) - top.vhd: wire phase adjustment signals, widen data buses - SweepConfigMem.xco: update BRAM width to 112 bits - FPGA.cpp/hpp: add sourcePhase parameter to WriteSweepConfig Phase formula: phase_degrees = (sourcePhase / M) * 360 For 180° shift: sourcePhase = M/2 Note: SweepConfigMem IP core must be regenerated before FPGA build. Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com> |
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| .. | ||
| FPGA | ||
| USB | ||
| algorithm.cpp | ||
| algorithm.hpp | ||
| delay.cpp | ||
| delay.hpp | ||
| Exti.cpp | ||
| Exti.hpp | ||
| Flash.cpp | ||
| Flash.hpp | ||
| Log.cpp | ||
| Log.h | ||
| max2871.cpp | ||
| max2871.hpp | ||
| Si5351C.cpp | ||
| Si5351C.hpp | ||
| stm.cpp | ||
| stm.hpp | ||