Roger Henderson 6c06293179 add per-point source PLL phase adjustment support ... Adds ability to set phase adjustment on Source PLL for each sweep point. When sourcePhase != 0, the FPGA executes a CDM toggle sequence after normal PLL register load to apply the specified phase offset. Changes: - MAX2871.vhd: add PHASE_ADJUST input and CDM toggle state machine - Sweep.vhd: extract phase from config, generate phase adjust signal - SPIConfig.vhd: handle 112-bit config data (was 96-bit) - top.vhd: wire phase adjustment signals, widen data buses - SweepConfigMem.xco: update BRAM width to 112 bits - FPGA.cpp/hpp: add sourcePhase parameter to WriteSweepConfig Phase formula: phase_degrees = (sourcePhase / M) * 360 For 180° shift: sourcePhase = M/2 Note: SweepConfigMem IP core must be regenerated before FPGA build. Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>		2026-01-31 16:57:10 +13:00
..
HelperTools/SignalIDSamplerates	Font-dependent width in toolbar	2020-11-23 13:02:56 +01:00
Integrationtests	HIL: more rigorous test of firmware update process	2025-05-31 15:14:19 +02:00
PC_Application	add SCPI API for dwell time	2026-01-27 18:24:05 +01:00
VNA_embedded	add per-point source PLL phase adjustment support	2026-01-31 16:57:10 +13:00
.gitignore	Some integration tests	2022-11-14 00:09:19 +01:00