Roger Henderson 6c06293179 add per-point source PLL phase adjustment support ... Adds ability to set phase adjustment on Source PLL for each sweep point. When sourcePhase != 0, the FPGA executes a CDM toggle sequence after normal PLL register load to apply the specified phase offset. Changes: - MAX2871.vhd: add PHASE_ADJUST input and CDM toggle state machine - Sweep.vhd: extract phase from config, generate phase adjust signal - SPIConfig.vhd: handle 112-bit config data (was 96-bit) - top.vhd: wire phase adjustment signals, widen data buses - SweepConfigMem.xco: update BRAM width to 112 bits - FPGA.cpp/hpp: add sourcePhase parameter to WriteSweepConfig Phase formula: phase_degrees = (sourcePhase / M) * 360 For 180° shift: sourcePhase = M/2 Note: SweepConfigMem IP core must be regenerated before FPGA build. Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>		2026-01-31 16:57:10 +13:00
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.gitignore	Missing ISE files	2020-10-28 18:03:54 +01:00
DSP48.xco	Basic DFT spectrum analysis working	2020-11-08 14:38:31 +01:00
DSP48.xise	Basic DFT spectrum analysis working	2020-11-08 14:38:31 +01:00
DSP_SLICE.xco	Basic DFT spectrum analysis working	2020-11-08 14:38:31 +01:00
DSP_SLICE.xise	Added stages to FPGA protocol	2022-04-01 23:01:22 +02:00
PLL.xco	Missing ISE files	2020-10-28 18:03:54 +01:00
PLL.xise	Added stages to FPGA protocol	2022-04-01 23:01:22 +02:00
result_bram.xco	Use full multiplier bitwidth for windowing + increased number of DFT bins	2020-11-08 14:38:31 +01:00
result_bram.xise	Added stages to FPGA protocol	2022-04-01 23:01:22 +02:00
SinCos.xco	Missing ISE files	2020-10-28 18:03:54 +01:00
SinCos.xise	Added stages to FPGA protocol	2022-04-01 23:01:22 +02:00
SweepConfigMem.xco	add per-point source PLL phase adjustment support	2026-01-31 16:57:10 +13:00
SweepConfigMem.xise	Added stages to FPGA protocol	2022-04-01 23:01:22 +02:00