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https://github.com/jankae/LibreVNA.git
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6c06293179
Adds ability to set phase adjustment on Source PLL for each sweep point. When sourcePhase != 0, the FPGA executes a CDM toggle sequence after normal PLL register load to apply the specified phase offset. Changes: - MAX2871.vhd: add PHASE_ADJUST input and CDM toggle state machine - Sweep.vhd: extract phase from config, generate phase adjust signal - SPIConfig.vhd: handle 112-bit config data (was 96-bit) - top.vhd: wire phase adjustment signals, widen data buses - SweepConfigMem.xco: update BRAM width to 112 bits - FPGA.cpp/hpp: add sourcePhase parameter to WriteSweepConfig Phase formula: phase_degrees = (sourcePhase / M) * 360 For 180° shift: sourcePhase = M/2 Note: SweepConfigMem IP core must be regenerated before FPGA build. Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com> |
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| .. | ||
| ipcore_dir | ||
| DFT.vhd | ||
| Flattop.dat | ||
| Hann.dat | ||
| Kaiser.dat | ||
| MAX2871.vhd | ||
| MCP33131.vhd | ||
| ResetDelay.vhd | ||
| Sampling.vhd | ||
| spi_slave.vhd | ||
| SPIConfig.vhd | ||
| Sweep.vhd | ||
| Synchronizer.vhd | ||
| Test_DFT.vhd | ||
| Test_MAX2871.vhd | ||
| Test_MCP33131.vhd | ||
| Test_PLL.vhd | ||
| Test_Sampling.vhd | ||
| Test_SinCos.vhd | ||
| Test_SPI.vhd | ||
| Test_SPICommands.vhd | ||
| Test_Window.vhd | ||
| Test_Windowing.vhd | ||
| top.bin | ||
| top.ucf | ||
| top.vhd | ||
| VNA.gise | ||
| VNA.xise | ||
| window.vhd | ||
| Windowing.vhd | ||