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https://github.com/jankae/LibreVNA.git
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69 lines
1.8 KiB
Plaintext
69 lines
1.8 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Tue Jun 7 10:30:52 2022
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:mult_gen:11.2
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = VHDL
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SET device = xc6slx9
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = tqg144
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -2
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SET verilogsim = false
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SET vhdlsim = true
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# END Project Options
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# BEGIN Select
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SELECT Multiplier xilinx.com:ip:mult_gen:11.2
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# END Select
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# BEGIN Parameters
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CSET ccmimp=Distributed_Memory
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CSET clockenable=true
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CSET component_name=AMMult
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CSET constvalue=129
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CSET internaluser=0
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CSET multiplier_construction=Use_Mults
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CSET multtype=Parallel_Multiplier
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CSET optgoal=Speed
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CSET outputwidthhigh=14
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CSET outputwidthlow=0
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CSET pipestages=1
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CSET portatype=Unsigned
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CSET portawidth=8
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CSET portbtype=Unsigned
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CSET portbwidth=7
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CSET roundpoint=0
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CSET sclrcepriority=SCLR_Overrides_CE
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CSET syncclear=false
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CSET use_custom_output_width=false
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CSET userounding=false
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CSET zerodetect=false
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2013-07-22T11:36:26Z
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# END Extra information
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GENERATE
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# CRC: b879ca8e
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