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https://github.com/jankae/LibreVNA.git
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385 lines
11 KiB
VHDL
385 lines
11 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:27:54 05/05/2020
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-- Design Name:
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-- Module Name: Sampling - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Sampling is
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Generic(CLK_CYCLES_PRE_DONE : integer;
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AUTOGAIN_SAMPLES : integer;
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AUTOGAIN_MAX : integer;
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AUTOGAIN_MIN : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
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PHASEINC : in STD_LOGIC_VECTOR(11 downto 0);
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PORT1 : in STD_LOGIC_VECTOR (17 downto 0);
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PORT2 : in STD_LOGIC_VECTOR (17 downto 0);
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REF : in STD_LOGIC_VECTOR (17 downto 0);
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ADC_START : out STD_LOGIC;
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NEW_SAMPLE : in STD_LOGIC;
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DONE : out STD_LOGIC;
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PRE_DONE : out STD_LOGIC;
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USEDGAIN : out STD_LOGIC_VECTOR (15 downto 0);
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START : in STD_LOGIC;
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SAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
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PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
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PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
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PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
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PORT2_Q : out STD_LOGIC_VECTOR (47 downto 0);
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REF_I : out STD_LOGIC_VECTOR (47 downto 0);
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REF_Q : out STD_LOGIC_VECTOR (47 downto 0);
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ACTIVE : out STD_LOGIC;
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PORT1_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
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PORT1_GAIN_READY : in STD_LOGIC;
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PORT1_AUTOGAIN : in STD_LOGIC;
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PORT2_GAIN : out STD_LOGIC_VECTOR (3 downto 0);
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PORT2_GAIN_READY : in STD_LOGIC;
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PORT2_AUTOGAIN : in STD_LOGIC);
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end Sampling;
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architecture Behavioral of Sampling is
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COMPONENT SinCos
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT DSP_SLICE
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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signal p1_I : std_logic_vector(47 downto 0);
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signal p1_Q : std_logic_vector(47 downto 0);
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signal p2_I : std_logic_vector(47 downto 0);
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signal p2_Q : std_logic_vector(47 downto 0);
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signal r_I : std_logic_vector(47 downto 0);
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signal r_Q : std_logic_vector(47 downto 0);
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signal clk_cnt : integer range 0 to 255;
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signal sample_cnt : integer range 0 to 131071;
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signal samples_to_take : integer range 0 to 131071;
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signal phase : std_logic_vector(11 downto 0);
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signal sine : std_logic_vector(15 downto 0);
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signal cosine : std_logic_vector(15 downto 0);
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signal mult_a : std_logic_vector(17 downto 0);
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signal mult_b : std_logic_vector(17 downto 0);
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signal mult_c : std_logic_vector(47 downto 0);
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signal mult_p : std_logic_vector(47 downto 0);
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signal mult_enable : std_logic;
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signal mult_accumulate : std_logic_vector(0 downto 0);
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signal p1_gain : std_logic_vector(3 downto 0);
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signal p2_gain : std_logic_vector(3 downto 0);
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signal p1_max : integer range -16384 to 16383;
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signal p2_max : integer range -16384 to 16383;
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signal p1_min : integer range -16384 to 16383;
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signal p2_min : integer range -16384 to 16383;
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signal autogain_cnt : integer range 0 to AUTOGAIN_SAMPLES + 1;
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signal autogain_changed : std_logic;
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type States is (Idle, Sampling, P1Q, P2I, P2Q, RI, RQ, SaveP1Q, SaveP2I, SaveP2Q, SaveRI, SaveRQ, Ready);
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signal state : States;
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begin
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-- Always fails for simulation, comment out
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-- assert (phase_inc * CLK_FREQ / (4096*CLK_DIV) = IF_FREQ)
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-- report "Phase increment not exact"
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-- severity FAILURE;
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LookupTable : SinCos
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PORT MAP (
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clk => CLK,
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phase_in => phase,
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cosine => cosine,
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sine => sine
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);
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Mult : DSP_SLICE
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PORT MAP (
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clk => CLK,
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ce => mult_enable,
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sel => mult_accumulate,
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a => mult_a,
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b => mult_b,
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c => mult_c,
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p => mult_p
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);
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-- sign extend b input of multiplier (sin/cos)
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mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
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PORT1_GAIN <= p1_gain;
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PORT2_GAIN <= p2_gain;
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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state <= Idle;
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ADC_START <= '0';
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '0';
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clk_cnt <= 0;
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sample_cnt <= 0;
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phase <= (others => '0');
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mult_enable <= '0';
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mult_accumulate <= "0";
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p1_gain <= "0000";
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p2_gain <= "0000";
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else
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-- when not idle, generate pulses for ADCs
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if state /= Idle then
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if clk_cnt = unsigned(ADC_PRESCALER) - 1 then
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if sample_cnt < samples_to_take then
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ADC_START <= '1';
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end if;
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clk_cnt <= 0;
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else
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clk_cnt <= clk_cnt + 1;
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ADC_START <= '0';
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end if;
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else
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ADC_START <= '0';
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end if;
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-- handle state transitions
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case state is
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when Idle =>
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sample_cnt <= 0;
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autogain_cnt <= 0;
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '0';
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clk_cnt <= 0;
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phase <= (others => '0');
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mult_enable <= '0';
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mult_accumulate <= "0";
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-- reset peak detector for autogain
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p1_max <= -16384;
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p2_max <= -16384;
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p1_min <= 16383;
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p2_min <= 16383;
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if START = '1' then
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state <= Sampling;
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samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
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end if;
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when Sampling =>
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '1';
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mult_enable <= '0';
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-- only accept new samples when the gain has been transferred to the PGA
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if NEW_SAMPLE = '1' and PORT1_GAIN_READY = '1' and PORT2_GAIN_READY = '1' then
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sample_cnt <= sample_cnt + 1;
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if autogain_cnt /= AUTOGAIN_SAMPLES + 1 then
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autogain_cnt <= autogain_cnt + 1;
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end if;
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autogain_changed <= '0';
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mult_enable <= '1';
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mult_a <= PORT1;
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mult_b(15 downto 0) <= cosine;
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mult_c <= p1_I;
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-- keep track of maximum value for autogain
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if to_integer(signed(PORT1)) > p1_max then
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p1_max <= to_integer(signed(PORT1));
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end if;
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if to_integer(signed(PORT1)) < p1_min then
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p1_min <= to_integer(signed(PORT1));
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end if;
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if to_integer(signed(PORT2)) > p2_max then
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p2_max <= to_integer(signed(PORT2));
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end if;
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if to_integer(signed(PORT2)) < p2_min then
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p2_min <= to_integer(signed(PORT2));
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end if;
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state <= P1Q;
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end if;
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when P1Q =>
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if autogain_cnt = AUTOGAIN_SAMPLES then
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-- check signal range and adjust gain if enabled and necessary
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if PORT1_AUTOGAIN = '1' and p1_max - p1_min > AUTOGAIN_MAX and p1_gain /= "0000" then
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-- signal too high, reduce gain
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autogain_changed <= '1';
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p1_gain <= std_logic_vector(unsigned(p1_gain) - 1);
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elsif PORT1_AUTOGAIN = '1' and p1_max - p1_min < AUTOGAIN_MIN and p1_gain /= "1000" then
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-- signal too low, increase gain
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autogain_changed <= '1';
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p1_gain <= std_logic_vector(unsigned(p1_gain) + 1);
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end if;
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if PORT2_AUTOGAIN = '1' and p2_max - p2_min > AUTOGAIN_MAX and p2_gain /= "0000" then
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-- signal too high, reduce gain
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autogain_changed <= '1';
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p2_gain <= std_logic_vector(unsigned(p2_gain) - 1);
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elsif PORT2_AUTOGAIN = '1' and p2_max - p2_min < AUTOGAIN_MIN and p2_gain /= "1000" then
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-- signal too low, increase gain
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autogain_changed <= '1';
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p2_gain <= std_logic_vector(unsigned(p2_gain) + 1);
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end if;
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end if;
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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mult_a <= PORT1;
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mult_b(15 downto 0) <= sine;
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mult_c <= p1_Q;
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state <= P2I;
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when P2I =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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mult_a <= PORT2;
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mult_b(15 downto 0) <= cosine;
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mult_c <= p2_I;
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state <= P2Q;
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if autogain_changed = '1' then
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-- reset autogain memory and restart sampling process
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p1_max <= -16384;
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p2_max <= -16384;
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p1_min <= 16383;
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p2_min <= 16383;
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sample_cnt <= 0;
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autogain_cnt <= 0;
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mult_accumulate <= "0";
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phase <= (others => '0');
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state <= Sampling;
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end if;
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when P2Q =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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mult_a <= PORT2;
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mult_b(15 downto 0) <= sine;
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mult_c <= p2_Q;
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state <= RI;
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when RI =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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mult_a <= REF;
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mult_b(15 downto 0) <= cosine;
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mult_c <= r_I;
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state <= RQ;
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when RQ =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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mult_a <= REF;
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mult_b(15 downto 0) <= sine;
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mult_c <= r_Q;
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-- first result is available
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p1_I <= mult_p;
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state <= SaveP1Q;
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when SaveP1Q =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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p1_Q <= mult_p;
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state <= SaveP2I;
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when SaveP2I =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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p2_I <= mult_p;
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state <= SaveP2Q;
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when SaveP2Q =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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p2_Q <= mult_p;
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state <= SaveRI;
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when SaveRI =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '1';
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r_I <= mult_p;
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state <= SaveRQ;
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when SaveRQ =>
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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mult_enable <= '0';
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r_Q <= mult_p;
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-- from now on accumulate results
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mult_accumulate <= "1";
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phase <= std_logic_vector(unsigned(phase) + unsigned(PHASEINC));
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if sample_cnt < samples_to_take then
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state <= Sampling;
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else
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state <= Ready;
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end if;
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when Ready =>
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ACTIVE <= '1';
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DONE <= '1';
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PRE_DONE <= '1';
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mult_enable <= '0';
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PORT1_I <= p1_I;
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PORT1_Q <= p1_Q;
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PORT2_I <= p2_I;
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PORT2_Q <= p2_Q;
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REF_I <= r_I;
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REF_Q <= r_Q;
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USEDGAIN <= "00000000" & p2_gain & p1_gain;
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state <= Idle;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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