jankae/LibreVNA
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538 commits 11 branches 20 tags 313 MiB
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6 commits

Author SHA1 Message Date
Jan Käberich 37d8474260 Added stages to FPGA protocol 2022-04-01 23:01:22 +02:00
Jan Käberich 7bc18881a5 Allow different source PLL power per sweep point, add power range to sweep 2021-07-09 22:25:54 +02:00
Jan Käberich 8b9b8265b9 Use full multiplier bitwidth for windowing + increased number of DFT bins 2020-11-08 14:38:31 +01:00
Jan Käberich ce475fa042 Basic DFT spectrum analysis working 2020-11-08 14:38:31 +01:00
Jan Käberich f889ec854b Test of DFT implementation in FPGA 2020-11-08 14:38:31 +01:00
Jan Käberich aee73f0c87 Missing ISE files 2020-10-28 18:03:54 +01:00